From patchwork Mon Sep 2 18:53:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeff Law X-Patchwork-Id: 1979723 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20230601 header.b=Js8TUqos; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4WyHwb24ycz1yXY for ; Tue, 3 Sep 2024 04:54:07 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 0B1C2385E45A for ; Mon, 2 Sep 2024 18:54:05 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-ot1-x330.google.com (mail-ot1-x330.google.com [IPv6:2607:f8b0:4864:20::330]) by sourceware.org (Postfix) with ESMTPS id 75FFE3858C66 for ; Mon, 2 Sep 2024 18:53:43 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 75FFE3858C66 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 75FFE3858C66 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::330 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1725303225; cv=none; b=nzKwTsMg74ZlVfPO3dRQTiWG/T6LBdGGxlrmPyOFHZ/Yz9mBcrEkFiOkbhxcB7fr1EN750LIfDr3eze8CTmYv2Ys9Rk7fP2rs0WbFw8lIV4oMNFhdFmTPSz/zRO7ZWrvE7f2zUhBm0hNQjBxEDGiVPEDielO/0fL4q+4UQS9+hQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1725303225; c=relaxed/simple; bh=cCgDBVL7/qkAwg3lMbnfsExIfz21QLWNyxYAb42kqIQ=; h=DKIM-Signature:Message-ID:Date:MIME-Version:Subject:To:From; b=HYN/nK3JV+bn5NFyNh2yq7k7EozpFJv95sz2npk2EvLJCuouW8nojdad3wSaNSivtWhZAchg6sDPOEMgzPGCJTlS/pdhtU/ENetwl9asAo6/zVTKXf8aUg4Ng4ylMaajgirGxII74+SlwqmDwaiOJXrXn9zlxB1aR7bOwpvQeSQ= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-ot1-x330.google.com with SMTP id 46e09a7af769-70f6a7c4dcdso1965261a34.1 for ; Mon, 02 Sep 2024 11:53:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1725303222; x=1725908022; darn=gcc.gnu.org; h=in-reply-to:from:to:references:content-language:subject:user-agent :mime-version:date:message-id:from:to:cc:subject:date:message-id :reply-to; bh=UU8zKmmScHXDTf3uMarpX7WDNl2azRUq3pt5BvpeXr8=; b=Js8TUqos60lscT02+KoBTpeJK2ZMEkpulLiaMnHvBbyAiGqB/OOpGM/kyuw11nhZLv t/mrFj/OkO9HC2b0KdkDRJTj8Rt793Xnd1QzXJ5TQMYDFMib4qBVLylo3mWWSPCDvnNR U80C6Skm0hD+9UVzJ1Glc4X8sb08PlfFuBtnjkJkj7LF48LZQEd5a8yTPUgWaB/Z+gxa mnh8LM0lZ2Q28YUf/UCO891vo3/kFjfhG5EjpyaIF8Kf3loW6A3UrvSU0fQhXUkw/Ae4 HPcb1yKMFYMHbx4y6w7f8+gFfjOFnaS5MUlok79gEYkU/UsAPrteo3pBz17E8LKtFCFt 9wMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1725303222; x=1725908022; h=in-reply-to:from:to:references:content-language:subject:user-agent :mime-version:date:message-id:x-gm-message-state:from:to:cc:subject :date:message-id:reply-to; bh=UU8zKmmScHXDTf3uMarpX7WDNl2azRUq3pt5BvpeXr8=; b=BSPY0YeA0xtO9GuZ96peSJzRhLqxvz6IWn3C6sy3qMq5wsWcrdXuov7UrRUiKyhPcG Id+qKj6BX46Ny/OHUzA0207N4nQZp0K779HuPGqKVALRo6UOTOW1GdkqbXfDtlUgKCF4 OoZsuybKO9fFouY4o+FuAtf9vLJ9snxGp+Rbjb12XziYA62KQ6gegbSI3sr4zryYSzyN y0Wknem+XhhvijIwC2iS1v+xgTgflLtkOveBOsd5pdsHFtTomUlocTeA6K3r9C6vT+fJ r5Ymzao0T6R8KI22LUEPZgO9Anc6+ryZ0SSLZ2fxlbFZf9/+ONf/l76DQ+5+B8rlvQwi /iHQ== X-Gm-Message-State: AOJu0YxVbehxPgs63FSlIaRzOksbRYzaJuAk5DGxkKottqOPMfs867/t 9SqIt4vGhgppId8aHG5yzi18y2fHhTol1wShWX6f+JABCqPBh/Tmz9054A== X-Google-Smtp-Source: AGHT+IHATnbARPO05qEUE+vzYuXvDciKNSkyUg9bD8oRU/9E0h6JcIUwOLBZsjhK4iTQP24DSHKhyw== X-Received: by 2002:a05:6358:9499:b0:1b5:fb38:5ed0 with SMTP id e5c5f4694b2df-1b7ef69be82mr918041355d.2.1725303222067; Mon, 02 Sep 2024 11:53:42 -0700 (PDT) Received: from [172.31.0.109] ([136.36.72.243]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7d22e9bf2dfsm6628329a12.63.2024.09.02.11.53.40 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 02 Sep 2024 11:53:41 -0700 (PDT) Message-ID: Date: Mon, 2 Sep 2024 12:53:38 -0600 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [to-be-committed] [RISC-V][PR target/115921] Improve reassociation for rv64 Content-Language: en-US References: <7c038242-8663-4d94-9175-ea23397faae2@gmail.com> To: "gcc-patches@gcc.gnu.org" From: Jeff Law In-Reply-To: <7c038242-8663-4d94-9175-ea23397faae2@gmail.com> X-Forwarded-Message-Id: <7c038242-8663-4d94-9175-ea23397faae2@gmail.com> X-Spam-Status: No, score=-8.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_NUMSUBJECT, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org This time with the RISC-V marker so the pre-commit testing system will pick it up... -------- Forwarded Message -------- Subject: [to-be-committed] [PR target/115921] Improve reassociation for rv64 Date: Mon, 2 Sep 2024 11:53:44 -0600 From: Jeff Law To: gcc-patches@gcc.gnu.org As Jovan pointed out in pr115921, we're not reassociating expressions like this on rv64: (x & 0x3e) << 12 It generates something like this: li a5,258048 slli a0,a0,12 and a0,a0,a5 We have a pattern that's designed to clean this up. Essentially reassociating the operations so that we don't need to load the constant resulting in something like this: andi a0,a0,63 slli a0,a0,12 That pattern wasn't working for certain constants due to its condition. The condition is trying to avoid cases where this kind of reassociation would hinder shadd generation on rv64. That condition was just written poorly. This patch tightens up that condition in a few ways. First, there's no need to worry about shadd cases if ZBA is not enabled. Second we can't use shadd if the shift value isn't 1, 2 or 3. Finally rather than open-coding one of the tests, we can use an existing operand predicate. The net is we'll start performing this transformation in more cases on rv64 while still avoiding reassociation if it would spoil shadd generation. Waiting on the pre-commit testing before taking any further action. Jeff diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 3289ed2155a..58b31658e0a 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -2925,7 +2925,9 @@ (define_insn_and_split "*si3_extend_mask" ;; for IOR/XOR. It probably doesn't matter for AND. ;; ;; We also don't want to do this if the immediate already fits in a simm12 -;; field. +;; field, or is a single bit operand, or when we might be able to generate +;; a shift-add sequence via the splitter in bitmanip.md +;; in bitmanip.md for masks that are a run of consecutive ones. (define_insn_and_split "_shift_reverse" [(set (match_operand:X 0 "register_operand" "=r") (any_bitwise:X (ashift:X (match_operand:X 1 "register_operand" "r") @@ -2934,9 +2936,9 @@ (define_insn_and_split "_shift_reverse" "(!SMALL_OPERAND (INTVAL (operands[3])) && SMALL_OPERAND (INTVAL (operands[3]) >> INTVAL (operands[2])) && popcount_hwi (INTVAL (operands[3])) > 1 - && (!TARGET_64BIT - || (exact_log2 ((INTVAL (operands[3]) >> INTVAL (operands[2])) + 1) - == -1)) + && (!(TARGET_64BIT && TARGET_ZBA) + || !consecutive_bits_operand (operands[3], VOIDmode) + || !imm123_operand (operands[2], VOIDmode)) && (INTVAL (operands[3]) & ((1ULL << INTVAL (operands[2])) - 1)) == 0)" "#" "&& 1" diff --git a/gcc/testsuite/gcc.target/riscv/pr115921.c b/gcc/testsuite/gcc.target/riscv/pr115921.c new file mode 100644 index 00000000000..e508e7ce790 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr115921.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gc_zba" { target { rv64 } } } */ +/* { dg-options "-O2 -march=rv32gc_zba" { target { rv32 } } } */ + +typedef unsigned long target_wide_uint_t; + +target_wide_uint_t test_ashift_and(target_wide_uint_t x) { + return (x & 0x3f) << 12; +} + +/* { dg-final { scan-assembler-times "\\sandi" 1 } } */ +/* { dg-final { scan-assembler-times "\\sslli" 1 } } */ +