From patchwork Thu Jun 29 13:55:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Preudhomme X-Patchwork-Id: 782297 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3wz1QD6lj3z9s3s for ; Thu, 29 Jun 2017 23:55:32 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="o/nFfYFK"; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:from:to:references:message-id:date:mime-version :in-reply-to:content-type; q=dns; s=default; b=f/HXkz2KloKY78ohW l1N+9MXoiDp822Vle9mXetUegDRgBFkEU7cvLViqzbMNG8YCxMSC3fUXsZbcGJyT OZkLzg3c+XTrgS8WxYb45PVne+J0+Epq1A8BTe54ja5/TzqijSMMekDUHR2ga7ur woSJHvI2rk7IVt7SE5aCq1+pKw= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:from:to:references:message-id:date:mime-version :in-reply-to:content-type; s=default; bh=z3Coh+nUgDriRCXK4t38ty+ WxpQ=; b=o/nFfYFK3FwE9X5UdeLL1VqvI2szMs4re7XJaCo1hN+4sxF97OLHlPG w0cmZ9R9+89eoWPFT6zDdpfmHzUF0zQ9wYNQpTMnVG5XX6GyPmiF3DMdmdWgQfv6 hk9kYi3ZVQwOZGV+ts9keMlsYnZIaHaU9h66XD+znDKt8Rqc28Mk= Received: (qmail 112114 invoked by alias); 29 Jun 2017 13:55:20 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 112091 invoked by uid 89); 29 Jun 2017 13:55:18 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_LAZY_DOMAIN_SECURITY, RCVD_IN_SORBS_SPAM, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=Hx-languages-length:1103 X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 29 Jun 2017 13:55:17 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 867E8344; Thu, 29 Jun 2017 06:55:16 -0700 (PDT) Received: from [10.2.206.52] (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C10973F557; Thu, 29 Jun 2017 06:55:15 -0700 (PDT) Subject: [PATCH 1/3, GCC/ARM] Add MIDR info for ARM Cortex-R7 and Cortex-R8 From: Thomas Preudhomme To: Kyrill Tkachov , Ramana Radhakrishnan , Richard Earnshaw , "gcc-patches@gcc.gnu.org" References: <9ab04ae2-a65a-11cc-dfaf-1a20a8137e4e@foss.arm.com> Message-ID: Date: Thu, 29 Jun 2017 14:55:14 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.1.1 MIME-Version: 1.0 In-Reply-To: <9ab04ae2-a65a-11cc-dfaf-1a20a8137e4e@foss.arm.com> X-IsSubscribed: yes Hi, The driver is missing MIDR information for processors ARM Cortex-R7 and Cortex-R8 to support -march/-mcpu/-mtune=native on the command line. This patch adds the missing information. ChangeLog entry is as follows: *** gcc/ChangeLog *** 2017-01-31 Thomas Preud'homme * config/arm/driver-arm.c (arm_cpu_table): Add entry for ARM Cortex-R7 and Cortex-R8 processors. Is this ok for master? Best regards, Thomas diff --git a/gcc/config/arm/driver-arm.c b/gcc/config/arm/driver-arm.c index b034f13fda63f5892bbd9879d72f4b02e2632d69..29873d57a1e45fd989f6ff01dd4a2ae7320d93bb 100644 --- a/gcc/config/arm/driver-arm.c +++ b/gcc/config/arm/driver-arm.c @@ -54,6 +54,8 @@ static struct vendor_cpu arm_cpu_table[] = { {"0xd09", "armv8-a+crc", "cortex-a73"}, {"0xc14", "armv7-r", "cortex-r4"}, {"0xc15", "armv7-r", "cortex-r5"}, + {"0xc17", "armv7-r", "cortex-r7"}, + {"0xc18", "armv7-r", "cortex-r8"}, {"0xc20", "armv6-m", "cortex-m0"}, {"0xc21", "armv6-m", "cortex-m1"}, {"0xc23", "armv7-m", "cortex-m3"},