From patchwork Sat Jun 21 16:32:34 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Glisse X-Patchwork-Id: 362462 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 12C0E140084 for ; Sun, 22 Jun 2014 02:32:59 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:in-reply-to:message-id:references :mime-version:content-type; q=dns; s=default; b=x6vDQGGzXxepBBvV /viqDb6Sy46bqF2pvAvaGzqIs8ScSiDPgU/k92/FgGlYVN/Uua/6F1o90of+2B8y 4pFZLZYy3RGNlRGHrJBuyMv0MvLt26PF/ePALwi08+oVAjCxPq2gtp4c8aqsU+WH RwBcm4PCsC7w1Xc/P9luq90p75M= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:in-reply-to:message-id:references :mime-version:content-type; s=default; bh=4Oc53tPwqS68UiDSNBo2nh tlfLI=; b=rzkXM5zrmwgK7IKrk3H8S1sXWoFBaqNRGpkOuzbaz4YMBUwL8Q4BH7 XM+diqlenJxsD62Jnl63Enu1YriFVDtP8bCr9mRYVU43vJC15ICt2F2Wyqr9o/P4 5fM4s3bwqn5hJnzzfeYXkba5efhWmEVCJj2iX/2cFVTVTScRPEck8= Received: (qmail 22746 invoked by alias); 21 Jun 2014 16:32:53 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 22735 invoked by uid 89); 21 Jun 2014 16:32:52 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-3.2 required=5.0 tests=AWL, BAYES_00, T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: mail3-relais-sop.national.inria.fr Received: from mail3-relais-sop.national.inria.fr (HELO mail3-relais-sop.national.inria.fr) (192.134.164.104) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (CAMELLIA256-SHA encrypted) ESMTPS; Sat, 21 Jun 2014 16:32:50 +0000 Received: from stedding.saclay.inria.fr ([193.55.250.194]) by mail3-relais-sop.national.inria.fr with ESMTP/TLS/AES128-SHA; 21 Jun 2014 18:32:35 +0200 Received: from glisse (helo=localhost) by stedding.saclay.inria.fr with local-esmtp (Exim 4.82_1-5b7a7c0-XX) (envelope-from ) id 1WyODS-0004rh-NU; Sat, 21 Jun 2014 18:32:34 +0200 Date: Sat, 21 Jun 2014 18:32:34 +0200 (CEST) From: Marc Glisse To: Uros Bizjak cc: "gcc-patches@gcc.gnu.org" Subject: Re: [i386] logical shift right in shrd In-Reply-To: Message-ID: References: User-Agent: Alpine 2.02 (DEB 1266 2009-07-14) MIME-Version: 1.0 On Sat, 21 Jun 2014, Uros Bizjak wrote: > On Fri, Jun 20, 2014 at 10:42 PM, Marc Glisse wrote: > >> as reported in PR 61503, there seems to be a typo in the shrd pattern. I >> think it is quite unlikely to cause any problem, because the pattern is 1 >> instruction too long for combine to recognize it (by the way, if someone has >> suggestions for PR 55583...). But it is still better to fix it. >> >> Bootstrap+testsuite on x86_64-linux-gnu. >> >> 2014-06-21 Marc Glisse >> >> PR target/61503 >> * config/i386/i386.md (x86_64_shrd, x86_shrd): Replace ashiftrt >> with lshiftrt. > > OK for mainline and 4.9. Thanks. Er, I am sorry, I don't know what happened, but when testing the backport to 4.9 I got an obvious failure in the testsuite, which I am sure should also happen on trunk, but somehow I didn't see it (I am almost sure I tested the right branch though). Anyway, here is an updated patch, that did pass bootstrap+testsuite both on trunk and 4.9. I haven't committed anything yet, is the new patch ok? 2014-06-21 Marc Glisse PR target/61503 * config/i386/i386.md (x86_64_shrd, x86_shrd, ix86_rotr3_doubleword): Replace ashiftrt with lshiftrt. Index: gcc/config/i386/i386.md =================================================================== --- gcc/config/i386/i386.md (revision 211865) +++ gcc/config/i386/i386.md (working copy) @@ -9601,37 +9601,37 @@ (match_operand: 1 "register_operand") (match_operand:QI 2 "nonmemory_operand"))) (clobber (reg:CC FLAGS_REG))]) (match_dup 3)] "TARGET_CMOVE" [(const_int 0)] "ix86_split_ (operands, operands[3], mode); DONE;") (define_insn "x86_64_shrd" [(set (match_operand:DI 0 "nonimmediate_operand" "+r*m") - (ior:DI (ashiftrt:DI (match_dup 0) + (ior:DI (lshiftrt:DI (match_dup 0) (match_operand:QI 2 "nonmemory_operand" "Jc")) (ashift:DI (match_operand:DI 1 "register_operand" "r") (minus:QI (const_int 64) (match_dup 2))))) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT" "shrd{q}\t{%s2%1, %0|%0, %1, %2}" [(set_attr "type" "ishift") (set_attr "prefix_0f" "1") (set_attr "mode" "DI") (set_attr "athlon_decode" "vector") (set_attr "amdfam10_decode" "vector") (set_attr "bdver1_decode" "vector")]) (define_insn "x86_shrd" [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m") - (ior:SI (ashiftrt:SI (match_dup 0) + (ior:SI (lshiftrt:SI (match_dup 0) (match_operand:QI 2 "nonmemory_operand" "Ic")) (ashift:SI (match_operand:SI 1 "register_operand" "r") (minus:QI (const_int 32) (match_dup 2))))) (clobber (reg:CC FLAGS_REG))] "" "shrd{l}\t{%s2%1, %0|%0, %1, %2}" [(set_attr "type" "ishift") (set_attr "prefix_0f" "1") (set_attr "mode" "SI") (set_attr "pent_pair" "np") @@ -10069,27 +10069,27 @@ (rotatert: (match_operand: 1 "register_operand" "0") (match_operand:QI 2 "" ""))) (clobber (reg:CC FLAGS_REG)) (clobber (match_scratch:DWIH 3 "=&r"))] "" "#" "reload_completed" [(set (match_dup 3) (match_dup 4)) (parallel [(set (match_dup 4) - (ior:DWIH (ashiftrt:DWIH (match_dup 4) (match_dup 2)) + (ior:DWIH (lshiftrt:DWIH (match_dup 4) (match_dup 2)) (ashift:DWIH (match_dup 5) (minus:QI (match_dup 6) (match_dup 2))))) (clobber (reg:CC FLAGS_REG))]) (parallel [(set (match_dup 5) - (ior:DWIH (ashiftrt:DWIH (match_dup 5) (match_dup 2)) + (ior:DWIH (lshiftrt:DWIH (match_dup 5) (match_dup 2)) (ashift:DWIH (match_dup 3) (minus:QI (match_dup 6) (match_dup 2))))) (clobber (reg:CC FLAGS_REG))])] { operands[6] = GEN_INT (GET_MODE_BITSIZE (mode)); split_double_mode (mode, &operands[0], 1, &operands[4], &operands[5]); }) (define_insn "*bmi2_rorx3_1"