From patchwork Fri Jun 20 20:42:14 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Glisse X-Patchwork-Id: 362344 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 25FAF140086 for ; Sat, 21 Jun 2014 06:42:26 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:mime-version:content-type; q=dns; s=default; b=JQkrnfrg+ZaL3NXpQHzUW258YKA/BakfBXrVSKg1w+pzFCVWd8 yq6COPxu+brqXDvDqn5BVaYqN8J93fsDhNZ/PBkcwDiQgm5zDhAru1r8vRFe52zO TQSjdKqQBxusKdkOGCPB0GHv74WcUZFwJO6SuF3v+eVsc+zxyHj1iZeXk= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:mime-version:content-type; s= default; bh=v+/sYII5QkbTnGuJCWUbwxm9lQo=; b=K2wuj9l6a2e24mC9c8SI CueFubAPN8yZGvu1x5zoLPZ2BBSbi674bncazRgN+SfchN6gSWlxzYLFRdP64yNn 3AoJ+wqEu5R2PwH07RhPMREfq8yhu4AYiyMCmVQJaCgAl1AFpUNtvcWaZ0r4zppO l9GA5opZcBV22S9x/0H5I2s= Received: (qmail 10523 invoked by alias); 20 Jun 2014 20:42:20 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 10510 invoked by uid 89); 20 Jun 2014 20:42:20 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-3.2 required=5.0 tests=AWL, BAYES_00, T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: mail3-relais-sop.national.inria.fr Received: from mail3-relais-sop.national.inria.fr (HELO mail3-relais-sop.national.inria.fr) (192.134.164.104) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (CAMELLIA256-SHA encrypted) ESMTPS; Fri, 20 Jun 2014 20:42:18 +0000 Received: from stedding.saclay.inria.fr ([193.55.250.194]) by mail3-relais-sop.national.inria.fr with ESMTP/TLS/AES128-SHA; 20 Jun 2014 22:42:15 +0200 Received: from glisse (helo=localhost) by stedding.saclay.inria.fr with local-esmtp (Exim 4.82_1-5b7a7c0-XX) (envelope-from ) id 1Wy5dW-0003aE-Vg; Fri, 20 Jun 2014 22:42:15 +0200 Date: Fri, 20 Jun 2014 22:42:14 +0200 (CEST) From: Marc Glisse To: gcc-patches@gcc.gnu.org cc: ubizjak@gmail.com Subject: [i386] logical shift right in shrd Message-ID: User-Agent: Alpine 2.02 (DEB 1266 2009-07-14) MIME-Version: 1.0 Hello, as reported in PR 61503, there seems to be a typo in the shrd pattern. I think it is quite unlikely to cause any problem, because the pattern is 1 instruction too long for combine to recognize it (by the way, if someone has suggestions for PR 55583...). But it is still better to fix it. Bootstrap+testsuite on x86_64-linux-gnu. 2014-06-21 Marc Glisse PR target/61503 * config/i386/i386.md (x86_64_shrd, x86_shrd): Replace ashiftrt with lshiftrt. Index: gcc/config/i386/i386.md =================================================================== --- gcc/config/i386/i386.md (revision 211856) +++ gcc/config/i386/i386.md (working copy) @@ -9601,37 +9601,37 @@ (match_operand: 1 "register_operand") (match_operand:QI 2 "nonmemory_operand"))) (clobber (reg:CC FLAGS_REG))]) (match_dup 3)] "TARGET_CMOVE" [(const_int 0)] "ix86_split_ (operands, operands[3], mode); DONE;") (define_insn "x86_64_shrd" [(set (match_operand:DI 0 "nonimmediate_operand" "+r*m") - (ior:DI (ashiftrt:DI (match_dup 0) + (ior:DI (lshiftrt:DI (match_dup 0) (match_operand:QI 2 "nonmemory_operand" "Jc")) (ashift:DI (match_operand:DI 1 "register_operand" "r") (minus:QI (const_int 64) (match_dup 2))))) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT" "shrd{q}\t{%s2%1, %0|%0, %1, %2}" [(set_attr "type" "ishift") (set_attr "prefix_0f" "1") (set_attr "mode" "DI") (set_attr "athlon_decode" "vector") (set_attr "amdfam10_decode" "vector") (set_attr "bdver1_decode" "vector")]) (define_insn "x86_shrd" [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m") - (ior:SI (ashiftrt:SI (match_dup 0) + (ior:SI (lshiftrt:SI (match_dup 0) (match_operand:QI 2 "nonmemory_operand" "Ic")) (ashift:SI (match_operand:SI 1 "register_operand" "r") (minus:QI (const_int 32) (match_dup 2))))) (clobber (reg:CC FLAGS_REG))] "" "shrd{l}\t{%s2%1, %0|%0, %1, %2}" [(set_attr "type" "ishift") (set_attr "prefix_0f" "1") (set_attr "mode" "SI") (set_attr "pent_pair" "np")