From patchwork Sat Oct 13 08:52:30 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Glisse X-Patchwork-Id: 191287 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id BD78A2C0080 for ; Sat, 13 Oct 2012 19:52:40 +1100 (EST) Comment: DKIM? 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If the strategy is all right, I could do the same for more operations (mul, div, ...). Something similar is also possible for V4SF (different pattern though), but probably not as useful. bootstrap+testsuite ok. 2012-10-13 Marc Glisse PR target/54855 gcc/ * config/i386/sse.md (*sse2_vmv2df3): New define_insn. gcc/testsuite/ * gcc.target/i386/pr54855.c: New testcase. Index: config/i386/sse.md =================================================================== --- config/i386/sse.md (revision 192420) +++ config/i386/sse.md (working copy) @@ -812,20 +812,38 @@ (const_int 1)))] "TARGET_SSE" "@ \t{%2, %0|%0, %2} v\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,avx") (set_attr "type" "sseadd") (set_attr "prefix" "orig,vex") (set_attr "mode" "")]) +(define_insn "*sse2_vmv2df3" + [(set (match_operand:V2DF 0 "register_operand" "=x,x") + (vec_concat:V2DF + (plusminus:DF + (vec_select:DF + (match_operand:V2DF 1 "register_operand" "0,x") + (parallel [(const_int 0)])) + (match_operand:DF 2 "nonimmediate_operand" "xm,xm")) + (vec_select:DF (match_dup 1) (parallel [(const_int 1)]))))] + "TARGET_SSE2" + "@ + sd\t{%2, %0|%0, %2} + vsd\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "isa" "noavx,avx") + (set_attr "type" "sseadd") + (set_attr "prefix" "orig,vex") + (set_attr "mode" "DF")]) + (define_expand "mul3" [(set (match_operand:VF 0 "register_operand") (mult:VF (match_operand:VF 1 "nonimmediate_operand") (match_operand:VF 2 "nonimmediate_operand")))] "TARGET_SSE" "ix86_fixup_binary_operands_no_copy (MULT, mode, operands);") (define_insn "*mul3" [(set (match_operand:VF 0 "register_operand" "=x,x") Index: testsuite/gcc.target/i386/pr54855.c =================================================================== --- testsuite/gcc.target/i386/pr54855.c (revision 0) +++ testsuite/gcc.target/i386/pr54855.c (revision 0) @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O -msse2" } */ + +typedef double vec __attribute__((vector_size(16))); + +vec f (vec x) +{ + x[0] += 2; + return x; +} + +vec g (vec x) +{ + x[0] -= 1; + return x; +} + +/* { dg-final { scan-assembler-not "mov" } } */