From patchwork Mon Nov 17 19:39:25 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Maciej W. Rozycki" X-Patchwork-Id: 411786 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 6B79714011D for ; Tue, 18 Nov 2014 06:39:48 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:mime-version:content-type; q=dns; s=default; b=uIzgjuXIsK7JrZ58DpCHoSKIEoj23OL0vmsSfnyS374FQOCap7 l/wQiXpOhO4a5+PnhGNAKBKLMFjH33q7M88C7DnrzJteb+ERDVNvpD4940j1TFBC 8tmvhKhU6ymHGlhAAX861wsNVlkPlYgkLnHHuz3+hY6B2++q+jKwYCzFE= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:mime-version:content-type; s= default; bh=zf1vrE4xrZy1TC8svDaMJzZxmP4=; b=MkIMPhtSy1pFqhRFkNlT Ia14ys8jzzj+vFRVQyy4YZ+wL4DCzXVqUyAbMhjZoHDJff07oZ54ckJI9CwwzevE fHSEql0e3bL8k00YBJsyMjSyLAC9oWm6A+tcCzPiZ5t80njo4SyWpRRAkS15+CDG 9yKstw0KLr1JfqbBtyvlKOY= Received: (qmail 32265 invoked by alias); 17 Nov 2014 19:39:40 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 32254 invoked by uid 89); 17 Nov 2014 19:39:40 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.0 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.2 X-HELO: relay1.mentorg.com Received: from relay1.mentorg.com (HELO relay1.mentorg.com) (192.94.38.131) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 17 Nov 2014 19:39:38 +0000 Received: from nat-ies.mentorg.com ([192.94.31.2] helo=SVR-IES-FEM-01.mgc.mentorg.com) by relay1.mentorg.com with esmtp id 1XqS96-0007d6-Ps from Maciej_Rozycki@mentor.com ; Mon, 17 Nov 2014 11:39:33 -0800 Received: from localhost (137.202.0.76) by SVR-IES-FEM-01.mgc.mentorg.com (137.202.0.104) with Microsoft SMTP Server (TLS) id 14.3.181.6; Mon, 17 Nov 2014 19:39:30 +0000 Date: Mon, 17 Nov 2014 19:39:25 +0000 From: "Maciej W. Rozycki" To: CC: Catherine Moore , Eric Christopher , Matthew Fortune Subject: [PATCH] microMIPS/GCC: Correct 64-bit instruction sizes Message-ID: User-Agent: Alpine 1.10 (DEB 962 2008-03-14) MIME-Version: 1.0 Hi, Noticed in an attempt to build a 64-bit microMIPS Linux kernel. None of the 64-bit operations have a short instruction encoding in the microMIPS instruction set. Despite that our code has been written such that the presence of a short encoding is assumed for both 32-bit and 64-bit operations. This leads to assembly warnings like: {standard input}: Assembler messages: {standard input}:146: Warning: wrong size instruction in a 16-bit branch delay slot {standard input}:544: Warning: wrong size instruction in a 16-bit branch delay slot {standard input}:1071: Warning: wrong size instruction in a 16-bit branch delay slot {standard input}:1088: Warning: wrong size instruction in a 16-bit branch delay slot {standard input}:1833: Warning: wrong size instruction in a 16-bit branch delay slot This is because code in question produced by GCC looks like: jals get_option # daddiu $4,$sp,16 #,, (in a `.set noreorder' fragment) and there is no short encoding for the DADDIU instruction available. At least two approaches are possible to address this problem, either by splitting the iterated patterns affected into separate 32-bit and 64-bit patterns, or by limiting the affected alternatives to 32-bit operations only. I found the latter less intrusive, with the use of an extra `compression' attribute value: `micromips32'. This is implemented with the change below, fixing the issues seen in 64-bit compilation. Code produced now looks like: jal get_option # daddiu $4,$sp,16 #,, instead. Some operations are operand size agnostic, these include LI16, MOVE16, and all the relevant logical instructions. These retain the `micromips' setting for the `compression' attribute. MOVEP is also operand size agnostic, but it must not be scheduled into a delay slot and it is therefore handled separately, with no `compression' attribute defined. Regression-tested with the mips-linux-gnu target and these multilibs: -EB -EB -mips16 -EB -mmicromips -EB -mabi=n32 -EB -mabi=64 and the -EL variants of same, with no changes in results. I have also checked that microMIPS shared glibc libraries have not changed when rebuilt with the updated compiler. OK to apply? 2014-11-14 Maciej W. Rozycki gcc/ * config/mips/mips.md (compression): Add `micromips32' setting. (enabled, length): Handle it. (shift_compression): Replace `micromips' with `micromips32' in the `compression' attribute. (*add3, sub3): Likewise. Maciej gcc-umips32-compression.diff Index: gcc-fsf-trunk-quilt/gcc/config/mips/mips.md =================================================================== --- gcc-fsf-trunk-quilt.orig/gcc/config/mips/mips.md 2014-11-14 18:34:25.000000000 +0000 +++ gcc-fsf-trunk-quilt/gcc/config/mips/mips.md 2014-11-14 20:56:20.278971795 +0000 @@ -429,7 +429,7 @@ (const_string "yes") (const_string "no"))) -(define_attr "compression" "none,all,micromips" +(define_attr "compression" "none,all,micromips32,micromips" (const_string "none")) (define_attr "enabled" "no,yes" @@ -440,7 +440,7 @@ || TARGET_O32_FP64A_ABI") (eq_attr "dword_mode" "yes")) (const_string "no") - (and (eq_attr "compression" "micromips") + (and (eq_attr "compression" "micromips32,micromips") (match_test "!TARGET_MICROMIPS")) (const_string "no")] (const_string "yes"))) @@ -526,7 +526,9 @@ ;; but there are special cases for branches (which must be handled here) ;; and for compressed single instructions. (define_attr "length" "" - (cond [(and (eq_attr "compression" "micromips,all") + (cond [(and (ior (eq_attr "compression" "micromips,all") + (and (eq_attr "compression" "micromips32") + (eq_attr "mode" "SI,SF"))) (eq_attr "dword_mode" "no") (match_test "TARGET_MICROMIPS")) (const_int 2) @@ -979,8 +981,8 @@ (xor "xori") (and "andi")]) -(define_code_attr shift_compression [(ashift "micromips") - (lshiftrt "micromips") +(define_code_attr shift_compression [(ashift "micromips32") + (lshiftrt "micromips32") (ashiftrt "none")]) ;; is the c.cond.fmt condition associated with a particular code. @@ -1163,7 +1165,7 @@ return "addiu\t%0,%1,%2"; } [(set_attr "alu_type" "add") - (set_attr "compression" "micromips,*,micromips,micromips,micromips,micromips,*") + (set_attr "compression" "micromips32,*,micromips32,micromips32,micromips32,micromips32,*") (set_attr "mode" "")]) (define_insn "*add3_mips16" @@ -1381,7 +1383,7 @@ "" "subu\t%0,%1,%2" [(set_attr "alu_type" "sub") - (set_attr "compression" "micromips,*") + (set_attr "compression" "micromips32,*") (set_attr "mode" "")]) (define_insn "*subsi3_extended"