Message ID | alpine.DEB.1.10.1311142232110.21686@tp.orcam.me.uk |
---|---|
State | Superseded |
Headers | show |
"Maciej W. Rozycki" <macro@codesourcery.com> writes: > 2013-11-14 Maciej W. Rozycki <macro@codesourcery.com> > > gcc/ > * config/mips/mips.h (ISA_HAS_FP4): Remove TARGET_FLOAT64 > restriction for ISA_MIPS32R2. > (ISA_HAS_FP_MADD4_MSUB4): Remove ISA_MIPS32R2 special-casing. > (ISA_HAS_NMADD4_NMSUB4): Likewise. > (ISA_HAS_FP_RECIP_RSQRT): Likewise. > (ISA_HAS_PREFETCHX): Redefine in terms of ISA_HAS_FP4. Nice. So the reasoning is that, after your RECIP.fmt patch, the only direct uses of ISA_HAS_FP4 for instruction selection are indexed loads and stores. That's why extending them to ISA_MIPS32R2 && !TARGET_FLOAT64 allows ISA_HAS_FP4 to be simplified. But if we keep: > @@ -906,16 +906,14 @@ struct mips_cpu_info { > #define GENERATE_MADD_MSUB (TARGET_IMADD && !TARGET_MIPS16) > > /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */ > -#define ISA_HAS_FP_MADD4_MSUB4 (ISA_HAS_FP4 \ > - || (ISA_MIPS32R2 && !TARGET_MIPS16)) > +#define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4 > > /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */ > #define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF > > /* ISA has floating-point nmadd and nmsub instructions > 'd = -((a * b) [+-] c)'. */ > -#define ISA_HAS_NMADD4_NMSUB4 (ISA_HAS_FP4 \ > - || (ISA_MIPS32R2 && !TARGET_MIPS16)) > +#define ISA_HAS_NMADD4_NMSUB4 ISA_HAS_FP4 then I think we should also have a macro like: /* ISA has indexed floating-point loads and stores (LWXC1, LDXC1, SWXC1 and SDXC1). */ #define ISA_HAS_LXC1_SXC1 ISA_HAS_FP4 and add: Note that this macro should only be used by other ISA_HAS_* macros. to the ISA_HAS_FP4 comment. OK with those changes, thanks. Richard
Index: gcc-fsf-trunk-quilt/gcc/config/mips/mips.h =================================================================== --- gcc-fsf-trunk-quilt.orig/gcc/config/mips/mips.h 2013-11-12 15:33:22.277646941 +0000 +++ gcc-fsf-trunk-quilt/gcc/config/mips/mips.h 2013-11-12 15:33:43.788707112 +0000 @@ -884,7 +884,7 @@ struct mips_cpu_info { FP madd and msub instructions, and the FP recip and recip sqrt instructions. */ #define ISA_HAS_FP4 ((ISA_MIPS4 \ - || (ISA_MIPS32R2 && TARGET_FLOAT64) \ + || ISA_MIPS32R2 \ || ISA_MIPS64 \ || ISA_MIPS64R2) \ && !TARGET_MIPS16) @@ -906,16 +906,14 @@ struct mips_cpu_info { #define GENERATE_MADD_MSUB (TARGET_IMADD && !TARGET_MIPS16) /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */ -#define ISA_HAS_FP_MADD4_MSUB4 (ISA_HAS_FP4 \ - || (ISA_MIPS32R2 && !TARGET_MIPS16)) +#define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4 /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */ #define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF /* ISA has floating-point nmadd and nmsub instructions 'd = -((a * b) [+-] c)'. */ -#define ISA_HAS_NMADD4_NMSUB4 (ISA_HAS_FP4 \ - || (ISA_MIPS32R2 && !TARGET_MIPS16)) +#define ISA_HAS_NMADD4_NMSUB4 ISA_HAS_FP4 /* ISA has floating-point nmadd and nmsub instructions 'c = -((a * b) [+-] c)'. */ @@ -926,8 +924,7 @@ struct mips_cpu_info { doubles are stored in pairs of FPRs, so for safety's sake, we apply this restriction to the MIPS IV ISA too. */ #define ISA_HAS_FP_RECIP_RSQRT(MODE) \ - (((ISA_HAS_FP4 \ - || (ISA_MIPS32R2 && !TARGET_MIPS16)) \ + ((ISA_HAS_FP4 \ && ((MODE) == SFmode \ || ((TARGET_FLOAT64 \ || !(ISA_MIPS4 \ @@ -1006,11 +1003,7 @@ struct mips_cpu_info { 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT. (prefx is a cop1x instruction, so can only be used if FP is enabled.) */ -#define ISA_HAS_PREFETCHX ((ISA_MIPS4 \ - || ISA_MIPS32R2 \ - || ISA_MIPS64 \ - || ISA_MIPS64R2) \ - && !TARGET_MIPS16) +#define ISA_HAS_PREFETCHX ISA_HAS_FP4 /* True if trunc.w.s and trunc.w.d are real (not synthetic) instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d