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Violators will be prosecuted; Tue, 10 Jan 2017 13:18:41 -0700 Received: from b01cxnp23034.gho.pok.ibm.com (b01cxnp23034.gho.pok.ibm.com [9.57.198.29]) by d03dlp02.boulder.ibm.com (Postfix) with ESMTP id 9FA403E40030; Tue, 10 Jan 2017 13:18:40 -0700 (MST) Received: from b01ledav004.gho.pok.ibm.com (b01ledav004.gho.pok.ibm.com [9.57.199.109]) by b01cxnp23034.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v0AKIem85702140; Tue, 10 Jan 2017 20:18:40 GMT Received: from b01ledav004.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1983411204B; Tue, 10 Jan 2017 15:18:40 -0500 (EST) Received: from BigMac.local (unknown [9.85.189.231]) by b01ledav004.gho.pok.ibm.com (Postfix) with ESMTP id D6F50112065; Tue, 10 Jan 2017 15:18:39 -0500 (EST) To: GCC Patches Cc: Segher Boessenkool , David Edelsohn From: Bill Schmidt Subject: [PATCH, rs6000] Fix PR79044 (ICE in swap optimization) Date: Tue, 10 Jan 2017 14:18:38 -0600 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.12; rv:45.0) Gecko/20100101 Thunderbird/45.6.0 MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Content-Scanned: Fidelis XPS MAILER x-cbid: 17011020-0012-0000-0000-000012EABB2D X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00006409; HX=3.00000240; KW=3.00000007; PH=3.00000004; SC=3.00000199; SDB=6.00805803; UDB=6.00392061; IPR=6.00583139; BA=6.00005042; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00013882; XFM=3.00000011; UTC=2017-01-10 20:18:42 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17011020-0013-0000-0000-00004A00E6A0 Message-Id: X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-01-10_16:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1612050000 definitions=main-1701100270 X-IsSubscribed: yes Hi, PR79044 reports a situation where swap optimization ICEs in GCC 6 and in trunk. The problem is that swap optimization doesn't properly recognize that element-reversing loads and stores (e.g., lxvw4x) cannot be treated as "swappable" instructions. These arise from the __builtin_vec_xl and __builtin_vec_xst interfaces that were added in GCC 6. The surrounding code is slightly different, so the fix is slightly different for the two releases. The fix is obvious, and bootstraps on powerpc64le-unknown-linux-gnu with no regressions. Are these patches ok for trunk and GCC 6, respectively? Thanks, Bill For current trunk: [gcc] 2017-01-10 Bill Schmidt PR target/79044 * config/rs6000/rs6000.c (insn_is_swappable_p): Mark element-reversing loads and stores as not swappable. [gcc/testsuite] 2017-01-10 Bill Schmidt PR target/79044 * gcc.target/powerpc/swaps-p8-26.c: New. Index: gcc/config/rs6000/rs6000.c =================================================================== --- gcc/config/rs6000/rs6000.c (revision 244274) +++ gcc/config/rs6000/rs6000.c (working copy) @@ -41344,7 +41344,10 @@ insn_is_swappable_p (swap_web_entry *insn_entry, r if (GET_CODE (body) == SET) { rtx rhs = SET_SRC (body); - gcc_assert (GET_CODE (rhs) == MEM); + /* Even without a swap, the RHS might be a vec_select for, say, + a byte-reversing load. */ + if (GET_CODE (rhs) != MEM) + return 0; if (GET_CODE (XEXP (rhs, 0)) == AND) return 0; @@ -41361,7 +41364,10 @@ insn_is_swappable_p (swap_web_entry *insn_entry, r && GET_CODE (SET_SRC (body)) != UNSPEC) { rtx lhs = SET_DEST (body); - gcc_assert (GET_CODE (lhs) == MEM); + /* Even without a swap, the LHS might be a vec_select for, say, + a byte-reversing store. */ + if (GET_CODE (lhs) != MEM) + return 0; if (GET_CODE (XEXP (lhs, 0)) == AND) return 0; Index: gcc/testsuite/gcc.target/powerpc/swaps-p8-26.c =================================================================== --- gcc/testsuite/gcc.target/powerpc/swaps-p8-26.c (revision 0) +++ gcc/testsuite/gcc.target/powerpc/swaps-p8-26.c (working copy) @@ -0,0 +1,21 @@ +/* { dg-do compile { target { powerpc64le-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-options "-mcpu=power8 -O3 " } */ +/* { dg-final { scan-assembler-times "lxvw4x" 2 } } */ +/* { dg-final { scan-assembler "stxvw4x" } } */ +/* { dg-final { scan-assembler-not "xxpermdi" } } */ + +/* Verify that swap optimization does not interfere with element-reversing + loads and stores. */ + +/* Test case to resolve PR79044. */ + +#include + +void pr79044 (float *x, float *y, float *z) +{ + vector float a = __builtin_vec_xl (0, x); + vector float b = __builtin_vec_xl (0, y); + vector float c = __builtin_vec_mul (a, b); + __builtin_vec_xst (c, 0, z); +} For GCC 6: [gcc] 2017-01-10 Bill Schmidt PR target/79044 * config/rs6000/rs6000.c (insn_is_swappable_p): Mark element-reversing loads and stores as not swappable. [gcc/testsuite] 2017-01-10 Bill Schmidt PR target/79044 * gcc.target/powerpc/swaps-p8-26.c: New. Index: gcc/config/rs6000/rs6000.c =================================================================== --- gcc/config/rs6000/rs6000.c (revision 244276) +++ gcc/config/rs6000/rs6000.c (working copy) @@ -38657,6 +38657,12 @@ insn_is_swappable_p (swap_web_entry *insn_entry, r { if (GET_CODE (body) == SET) { + rtx rhs = SET_SRC (body); + /* Even without a swap, the RHS might be a vec_select for, say, + a byte-reversing load. */ + if (GET_CODE (rhs) != MEM) + return 0; + *special = SH_NOSWAP_LD; return 1; } @@ -38668,6 +38674,12 @@ insn_is_swappable_p (swap_web_entry *insn_entry, r { if (GET_CODE (body) == SET && GET_CODE (SET_SRC (body)) != UNSPEC) { + rtx lhs = SET_DEST (body); + /* Even without a swap, the LHS might be a vec_select for, say, + a byte-reversing store. */ + if (GET_CODE (lhs) != MEM) + return 0; + *special = SH_NOSWAP_ST; return 1; } Index: gcc/testsuite/gcc.target/powerpc/swaps-p8-26.c =================================================================== --- gcc/testsuite/gcc.target/powerpc/swaps-p8-26.c (revision 0) +++ gcc/testsuite/gcc.target/powerpc/swaps-p8-26.c (working copy) @@ -0,0 +1,21 @@ +/* { dg-do compile { target { powerpc64le-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-options "-mcpu=power8 -O3 " } */ +/* { dg-final { scan-assembler-times "lxvw4x" 2 } } */ +/* { dg-final { scan-assembler "stxvw4x" } } */ +/* { dg-final { scan-assembler-not "xxpermdi" } } */ + +/* Verify that swap optimization does not interfere with element-reversing + loads and stores. */ + +/* Test case to resolve PR79044. */ + +#include + +void pr79044 (float *x, float *y, float *z) +{ + vector float a = __builtin_vec_xl (0, x); + vector float b = __builtin_vec_xl (0, y); + vector float c = __builtin_vec_mul (a, b); + __builtin_vec_xst (c, 0, z); +}