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Mon, 24 Oct 2022 03:14:26 +0000 Received: from d06av22.portsmouth.uk.ibm.com (d06av22.portsmouth.uk.ibm.com [9.149.105.58]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 29O3ENH453674482 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 24 Oct 2022 03:14:23 GMT Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 15AC54C044; Mon, 24 Oct 2022 03:14:23 +0000 (GMT) Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D53734C040; Mon, 24 Oct 2022 03:14:20 +0000 (GMT) Received: from [9.197.241.70] (unknown [9.197.241.70]) by d06av22.portsmouth.uk.ibm.com (Postfix) with ESMTP; Mon, 24 Oct 2022 03:14:20 +0000 (GMT) Message-ID: Date: Mon, 24 Oct 2022 11:14:20 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.4.0 To: gcc-patches Subject: [PATCH-2, rs6000] Reverse V8HI on Power8 by vector rotation [PR100866] X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 6M-yzrOqxxLhB0fYbaAFmule_BqzM3hR X-Proofpoint-ORIG-GUID: I_cz-pd52bh9VJt9DqI9FyBkH8-GJuw0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-21_04,2022-10-21_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 suspectscore=0 lowpriorityscore=0 priorityscore=1501 phishscore=0 clxscore=1011 mlxscore=0 malwarescore=0 impostorscore=0 spamscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2210240018 X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: HAO CHEN GUI via Gcc-patches From: HAO CHEN GUI Reply-To: HAO CHEN GUI Cc: Peter Bergner , David , Segher Boessenkool Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" Hi, This patch implements V8HI byte reverse on Power8 by vector rotation. It should be effecient than orignial vector permute. The patch comes from Xionghu's comments in PR. I just added a test case for it. Bootstrapped and tested on ppc64 Linux BE and LE with no regressions. Is this okay for trunk? Any recommendations? Thanks a lot. ChangeLog 2022-10-24 Xionghu Luo gcc/ PR target/100866 * config/rs6000/altivec.md: (*altivec_vrl): Named to... (altivec_vrl): ...this. * config/rs6000/vsx.md (revb_): Call vspltish and vrlh when target is Power8 and mode is V8HI. gcc/testsuite/ PR target/100866 * gcc.target/powerpc/pr100866-2.c: New. patch.diff diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 2c4940f2e21..84660073f32 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -1875,7 +1875,7 @@ (define_insn "altivec_vpkuum_direct" } [(set_attr "type" "vecperm")]) -(define_insn "*altivec_vrl" +(define_insn "altivec_vrl" [(set (match_operand:VI2 0 "register_operand" "=v") (rotate:VI2 (match_operand:VI2 1 "register_operand" "v") (match_operand:VI2 2 "register_operand" "v")))] diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index e226a93bbe5..34662a7252d 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -6092,12 +6092,21 @@ (define_expand "revb_" emit_insn (gen_p9_xxbr_ (operands[0], operands[1])); else { - /* Want to have the elements in reverse order relative - to the endian mode in use, i.e. in LE mode, put elements - in BE order. */ - rtx sel = swap_endian_selector_for_mode(mode); - emit_insn (gen_altivec_vperm_ (operands[0], operands[1], - operands[1], sel)); + if (mode == V8HImode) + { + rtx splt = gen_reg_rtx (V8HImode); + emit_insn (gen_altivec_vspltish (splt, GEN_INT (8))); + emit_insn (gen_altivec_vrlh (operands[0], operands[1], splt)); + } + else + { + /* Want to have the elements in reverse order relative + to the endian mode in use, i.e. in LE mode, put elements + in BE order. */ + rtx sel = swap_endian_selector_for_mode (mode); + emit_insn (gen_altivec_vperm_ (operands[0], operands[1], + operands[1], sel)); + } } DONE; diff --git a/gcc/testsuite/gcc.target/powerpc/pr100866-2.c b/gcc/testsuite/gcc.target/powerpc/pr100866-2.c new file mode 100644 index 00000000000..4357d1beb09 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr100866-2.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power8" } */ +/* { dg-final { scan-assembler {\mvspltish\M} } } */ +/* { dg-final { scan-assembler {\mvrlh\M} } } */ + +#include + +vector unsigned short revb(vector unsigned short a) +{ + return vec_revb(a); +} +