diff --git a/gcc/config/sparc/sparc.cc b/gcc/config/sparc/sparc.cc
index 4bc249da825e..353837d73e55 100644
--- a/gcc/config/sparc/sparc.cc
+++ b/gcc/config/sparc/sparc.cc
@@ -697,7 +697,6 @@ static const char *sparc_mangle_type (const_tree);
 static void sparc_trampoline_init (rtx, tree, rtx);
 static machine_mode sparc_preferred_simd_mode (scalar_mode);
 static reg_class_t sparc_preferred_reload_class (rtx x, reg_class_t rclass);
-static bool sparc_lra_p (void);
 static bool sparc_print_operand_punct_valid_p (unsigned char);
 static void sparc_print_operand (FILE *, rtx, int);
 static void sparc_print_operand_address (FILE *, machine_mode, rtx);
@@ -921,9 +920,6 @@ char sparc_hard_reg_printed[8];
 #define TARGET_MANGLE_TYPE sparc_mangle_type
 #endif
 
-#undef TARGET_LRA_P
-#define TARGET_LRA_P sparc_lra_p
-
 #undef TARGET_LEGITIMATE_ADDRESS_P
 #define TARGET_LEGITIMATE_ADDRESS_P sparc_legitimate_address_p
 
@@ -1957,10 +1953,6 @@ sparc_option_override (void)
   if (TARGET_ARCH32)
     target_flags &= ~MASK_STACK_BIAS;
 
-  /* Use LRA instead of reload, unless otherwise instructed.  */
-  if (!(target_flags_explicit & MASK_LRA))
-    target_flags |= MASK_LRA;
-
   /* Enable applicable errata workarounds for LEON3FT.  */
   if (sparc_fix_ut699 || sparc_fix_ut700 || sparc_fix_gr712rc)
     {
@@ -13286,14 +13278,6 @@ sparc_preferred_reload_class (rtx x, reg_class_t rclass)
   return rclass;
 }
 
-/* Return true if we use LRA instead of reload pass.  */
-
-static bool
-sparc_lra_p (void)
-{
-  return TARGET_LRA;
-}
-
 /* Output a wide multiply instruction in V8+ mode.  INSN is the instruction,
    OPERANDS are its operands and OPCODE is the mnemonic to be used.  */
 
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index 736307926f9a..96c542c6ab6e 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -265,12 +265,8 @@ (define_attr "isa" "v7,v8,v9,sparclet"
 (define_attr "cpu_feature" "none,fpu,fpunotv9,v9,vis,vis3,vis4,vis4b"
   (const_string "none"))
 
-(define_attr "lra" "disabled,enabled"
-  (const_string "enabled"))
-
 (define_attr "enabled" ""
-  (cond [(eq_attr "cpu_feature" "none")
-           (cond [(eq_attr "lra" "disabled") (symbol_ref "!TARGET_LRA")] (const_int 1))
+  (cond [(eq_attr "cpu_feature" "none") (const_int 1)
          (eq_attr "cpu_feature" "fpu") (symbol_ref "TARGET_FPU")
          (eq_attr "cpu_feature" "fpunotv9") (symbol_ref "TARGET_FPU && !TARGET_V9")
          (eq_attr "cpu_feature" "v9") (symbol_ref "TARGET_V9")
@@ -1867,8 +1863,7 @@ (define_insn "*movdi_insn_sp32"
    (set_attr "subtype" "*,*,regular,*,regular,*,*,*,*,*,*,*,*,*,*,*,*,*,double,double")
    (set_attr "length" "*,2,*,*,*,*,2,2,*,*,2,2,*,2,2,2,*,*,*,*")
    (set_attr "fptype" "*,*,*,*,*,*,*,*,*,*,*,*,double,*,*,*,*,*,double,double")
-   (set_attr "cpu_feature" "v9,*,*,*,*,*,*,*,fpu,fpu,fpu,fpu,v9,fpunotv9,vis3,vis3,fpu,fpu,vis,vis")
-   (set_attr "lra" "*,*,disabled,disabled,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*")])
+   (set_attr "cpu_feature" "v9,*,*,*,*,*,*,*,fpu,fpu,fpu,fpu,v9,fpunotv9,vis3,vis3,fpu,fpu,vis,vis")])
 
 (define_insn "*movdi_insn_sp64"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r, m, r,*e,?*e,?*e,  m,b,b")
@@ -2496,8 +2491,7 @@ (define_insn "*movdf_insn_sp32"
    (set_attr "subtype" "*,*,double,double,*,*,*,*,*,*,regular,*,*,*,*,regular,*")
    (set_attr "length" "*,2,*,*,*,2,2,2,*,*,*,*,2,2,2,*,*")
    (set_attr "fptype" "*,*,double,double,double,*,*,*,*,*,*,*,*,*,*,*,*")
-   (set_attr "cpu_feature" "v9,*,vis,vis,v9,fpunotv9,vis3,vis3,fpu,fpu,*,*,fpu,fpu,*,*,*")
-   (set_attr "lra" "*,*,*,*,*,*,*,*,*,*,disabled,disabled,*,*,*,*,*")])
+   (set_attr "cpu_feature" "v9,*,vis,vis,v9,fpunotv9,vis3,vis3,fpu,fpu,*,*,fpu,fpu,*,*,*")])
 
 (define_insn "*movdf_insn_sp64"
   [(set (match_operand:DF 0 "nonimmediate_operand" "=b,b,e,*r, e,  e,m, *r,*r,  m,*r")
@@ -8526,8 +8520,7 @@ (define_insn "*mov<VM64:mode>_insn_sp32"
   [(set_attr "type" "store,*,visl,visl,vismv,*,*,fpload,fpstore,load,store,*,*,*,load,store")
    (set_attr "subtype" "*,*,double,double,double,*,*,*,*,regular,*,*,*,*,regular,*")
    (set_attr "length" "*,2,*,*,*,2,2,*,*,*,*,2,2,2,*,*")
-   (set_attr "cpu_feature" "*,*,vis,vis,vis,vis3,vis3,*,*,*,*,*,*,*,*,*")
-   (set_attr "lra" "*,*,*,*,*,*,*,*,*,disabled,disabled,*,*,*,*,*")])
+   (set_attr "cpu_feature" "*,*,vis,vis,vis,vis3,vis3,*,*,*,*,*,*,*,*,*")])
 
 (define_split
   [(set (match_operand:VM64 0 "register_operand" "")
diff --git a/gcc/config/sparc/sparc.opt b/gcc/config/sparc/sparc.opt
index afede3f40ce6..235974c16a83 100644
--- a/gcc/config/sparc/sparc.opt
+++ b/gcc/config/sparc/sparc.opt
@@ -57,10 +57,6 @@ msoft-quad-float
 Target RejectNegative InverseMask(HARD_QUAD)
 Do not use hardware quad fp instructions.
 
-mlra
-Target Mask(LRA)
-Enable Local Register Allocation.
-
 mv8plus
 Target Mask(V8PLUS)
 Compile for V8+ ABI.
diff --git a/gcc/config/sparc/sparc.opt.urls b/gcc/config/sparc/sparc.opt.urls
index 24cc22e4cbc7..2a6ffa258e08 100644
--- a/gcc/config/sparc/sparc.opt.urls
+++ b/gcc/config/sparc/sparc.opt.urls
@@ -24,9 +24,6 @@ UrlSuffix(gcc/SPARC-Options.html#index-mhard-quad-float)
 msoft-quad-float
 UrlSuffix(gcc/SPARC-Options.html#index-msoft-quad-float)
 
-mlra
-UrlSuffix(gcc/SPARC-Options.html#index-mlra-3)
-
 mv8plus
 UrlSuffix(gcc/SPARC-Options.html#index-mv8plus)
 
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 0db754c888a6..8437b2029ede 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1414,8 +1414,7 @@ See RS/6000 and PowerPC Options.
 -mvis4  -mno-vis4  -mvis4b  -mno-vis4b
 -mcbcond  -mno-cbcond  -mfmaf  -mno-fmaf  -mfsmuld  -mno-fsmuld
 -mpopc  -mno-popc  -msubxc  -mno-subxc
--mfix-at697f  -mfix-ut699  -mfix-ut700  -mfix-gr712rc
--mlra  -mno-lra}
+-mfix-at697f  -mfix-ut699  -mfix-ut700  -mfix-gr712rc}
 
 @emph{System V Options}
 @gccoptlist{-Qy  -Qn  -YP,@var{paths}  -Ym,@var{dir}}
@@ -33564,13 +33563,6 @@ between the two sides of function calls, as per the 32-bit ABI@.
 The default is @option{-mno-std-struct-return}.  This option has no effect
 in 64-bit mode.
 
-@opindex mlra
-@opindex mno-lra
-@item -mlra
-@itemx -mno-lra
-Enable Local Register Allocation.  This is the default for SPARC since GCC 7
-so @option{-mno-lra} needs to be passed to get old Reload.
-
 @opindex mcpu
 @item -mcpu=@var{cpu_type}
 Set the instruction set, register set, and instruction scheduling parameters
