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a=ed25519-sha256; c=relaxed/relaxed; t=1709383849; s=strato-dkim-0003; d=gjlay.de; h=Subject:To:From:Date:Message-ID:Cc:Date:From:Subject:Sender; bh=62bUxLR8tjGYvZ1anDIJTc2vF4t9ly7Sw4PjrXsP5dI=; b=FBoeC97E5fGVeWh+Ap1mb+BvRR22sPA28hvgEMFdCiG2nb0Mv8RNQCCJ/Gw0uAFpIn HOPjHMz2jBroAllIdmAA== X-RZG-AUTH: ":LXoWVUeid/7A29J/hMvvT3koxZnKT7Qq0xotTetVnKkSgcSjpmy9KwoMJ/K0VA==" Received: from [192.168.2.102] by smtp.strato.de (RZmta 50.2.0 DYNA|AUTH) with ESMTPSA id Jdfd10022Com34O (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256 bits)) (Client did not present a certificate) for ; Sat, 2 Mar 2024 13:50:48 +0100 (CET) Message-ID: Date: Sat, 2 Mar 2024 13:50:48 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Content-Language: en-US From: Georg-Johann Lay To: "gcc-patches@gcc.gnu.org" Subject: [patch,avr,applied] Avoid magic numbers for register numbers. X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org There are some places where avr.cc uses magic numbers like 17 that are actually register numbers. This patch defines constants like REG_17 and uses them instead of the magic numbers when a register number is meant. Johann --- AVR: Use REG_ constants instead of magic numbers . There are some places where avr.cc uses magic numbers like 17 that are actually register numbers. This patch defines constants like REG_17 and uses them instead of the magic numbers when a register number is meant. gcc/ * config/avr/avr.md (REG_0, ... REG_36): New define_constants. * config/avr/avr.cc: Use them instead of magic numbers when it means a register number. diff --git a/gcc/config/avr/avr.cc b/gcc/config/avr/avr.cc index e312ddfbff4..5c71c7f8c0d 100644 --- a/gcc/config/avr/avr.cc +++ b/gcc/config/avr/avr.cc @@ -171,10 +171,10 @@ static bool avr_rtx_costs (rtx, machine_mode, int, int, int *, bool); /* Allocate registers from r25 to r8 for parameters for function calls. */ -#define FIRST_CUM_REG 26 +#define FIRST_CUM_REG REG_26 /* Last call saved register */ -#define LAST_CALLEE_SAVED_REG (AVR_TINY ? 19 : 17) +#define LAST_CALLEE_SAVED_REG (AVR_TINY ? REG_19 : REG_17) /* Implicit target register of LPM instruction (R0) */ extern GTY(()) rtx lpm_reg_rtx; @@ -197,8 +197,8 @@ extern GTY(()) rtx cc_reg_rtx; rtx cc_reg_rtx; /* RTXs for all general purpose registers as QImode */ -extern GTY(()) rtx all_regs_rtx[32]; -rtx all_regs_rtx[32]; +extern GTY(()) rtx all_regs_rtx[REG_32]; +rtx all_regs_rtx[REG_32]; /* SREG, the processor status */ extern GTY(()) rtx sreg_rtx; @@ -542,7 +542,7 @@ avr_casei_sequence_check_operands (rtx *xop) if (AVR_HAVE_EIJMP_EICALL // The last clobber op of the tablejump. - && xop[8] == all_regs_rtx[24]) + && xop[8] == all_regs_rtx[REG_24]) { // $6 is: (subreg:SI ($5) 0) sub_5 = xop[6]; @@ -1171,7 +1171,7 @@ avr_init_machine_status (void) void avr_init_expanders (void) { - for (int regno = 0; regno < 32; regno ++) + for (int regno = REG_0; regno < REG_32; regno ++) all_regs_rtx[regno] = gen_rtx_REG (QImode, regno); lpm_reg_rtx = all_regs_rtx[LPM_REGNO]; @@ -1549,7 +1549,7 @@ avr_regs_to_save (HARD_REG_SET *set) || cfun->machine->is_OS_main) return 0; - for (int reg = 0; reg < 32; reg++) + for (int reg = REG_0; reg < REG_32; reg++) { /* Do not push/pop __tmp_reg__, __zero_reg__, as well as any global register variables. */ @@ -2300,9 +2300,9 @@ avr_pass_fuse_add::execute (function *func) FOR_EACH_BB_FN (bb, func) { - Ldi_Insn prev_ldi_insns[32]; - Add_Insn prev_add_insns[32]; - Mem_Insn prev_mem_insns[32]; + Ldi_Insn prev_ldi_insns[REG_32]; + Add_Insn prev_add_insns[REG_32]; + Mem_Insn prev_mem_insns[REG_32]; rtx_insn *insn, *curr; avr_dump ("\n;; basic block %d\n\n", bb->index); @@ -2484,7 +2484,7 @@ avr_incoming_return_addr_rtx (void) static int avr_hregs_split_reg (HARD_REG_SET *set) { - for (int regno = 0; regno < 32; regno++) + for (int regno = REG_0; regno < REG_32; regno++) if (TEST_HARD_REG_BIT (*set, regno)) { // Don't remove a register from *SET which might indicate that @@ -2620,9 +2620,9 @@ avr_prologue_setup_frame (HOST_WIDE_INT size, HARD_REG_SET set) first_reg = (LAST_CALLEE_SAVED_REG + 1) - (live_seq - 2); - for (reg = 29, offset = -live_seq + 1; + for (reg = REG_29, offset = -live_seq + 1; reg >= first_reg; - reg = (reg == 28 ? LAST_CALLEE_SAVED_REG : reg - 1), ++offset) + reg = (reg == REG_28 ? LAST_CALLEE_SAVED_REG : reg - 1), ++offset) { rtx m, r; @@ -2636,7 +2636,7 @@ avr_prologue_setup_frame (HOST_WIDE_INT size, HARD_REG_SET set) } else /* !minimize */ { - for (int reg = 0; reg < 32; ++reg) + for (int reg = REG_0; reg < REG_32; ++reg) if (TEST_HARD_REG_BIT (set, reg)) emit_push_byte (reg, true); @@ -3795,7 +3795,7 @@ avr_print_operand (FILE *file, rtx x, int code) { if (x == zero_reg_rtx) fprintf (file, "__zero_reg__"); - else if (code == 'r' && REGNO (x) < 32) + else if (code == 'r' && REGNO (x) < REG_32) fprintf (file, "%d", (int) REGNO (x)); else fprintf (file, "%s", reg_names[REGNO (x) + abcd]); @@ -4136,7 +4136,9 @@ avr_asm_final_postscan_insn (FILE *stream, rtx_insn *insn, rtx *, int) int avr_function_arg_regno_p (int r) { - return AVR_TINY ? IN_RANGE (r, 20, 25) : IN_RANGE (r, 8, 25); + return AVR_TINY + ? IN_RANGE (r, REG_20, REG_25) + : IN_RANGE (r, REG_8, REG_25); } @@ -4148,7 +4150,7 @@ void avr_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype, rtx libname, tree fndecl ATTRIBUTE_UNUSED) { - cum->nregs = AVR_TINY ? 6 : 18; + cum->nregs = 1 + AVR_TINY ? REG_25 - REG_20 : REG_25 - REG_8; cum->regno = FIRST_CUM_REG; cum->has_stack_args = 0; if (!libname && stdarg_p (fntype)) @@ -4216,7 +4218,7 @@ avr_function_arg_advance (cumulative_args_t cum_v, a function must not pass arguments in call-saved regs in order to get tail-called. */ - if (cum->regno >= 8 + if (cum->regno >= REG_8 && cum->nregs >= 0 && !call_used_or_fixed_reg_p (cum->regno)) { @@ -4233,7 +4235,7 @@ avr_function_arg_advance (cumulative_args_t cum_v, user has fixed a GPR needed to pass an argument, an (implicit) function call will clobber that fixed register. See PR45099 for an example. */ - if (cum->regno >= 8 + if (cum->regno >= REG_8 && cum->nregs >= 0) { for (int regno = cum->regno; regno < cum->regno + bytes; regno++) @@ -4348,7 +4350,7 @@ avr_find_unused_d_reg (rtx_insn *insn, rtx exclude) bool isr_p = (avr_interrupt_function_p (current_function_decl) || avr_signal_function_p (current_function_decl)); - for (int regno = 16; regno < 32; regno++) + for (int regno = REG_16; regno < REG_32; regno++) { rtx reg = all_regs_rtx[regno]; @@ -7117,7 +7119,7 @@ avr_out_compare64 (rtx_insn *insn, rtx *op, int *plen) { rtx xop[3]; - xop[0] = gen_rtx_REG (DImode, 18); + xop[0] = gen_rtx_REG (DImode, ACC_A); xop[1] = op[0]; xop[2] = op[1]; @@ -7340,7 +7342,7 @@ out_shift_with_cnt (const char *templ, rtx_insn *insn, rtx operands[], /* No scratch register available, use one from LD_REGS (saved in __tmp_reg__) that doesn't overlap with registers to shift. */ - op[3] = all_regs_rtx[((REGNO (op[0]) - 1) & 15) + 16]; + op[3] = all_regs_rtx[((REGNO (op[0]) - 1) & 15) + REG_16]; op[4] = tmp_reg_rtx; saved_in_tmp = true; @@ -13712,8 +13714,8 @@ output_reload_in_const (rtx *op, rtx clobber_reg, int *len, bool clear_p) /* (REG:SI 14) is special: It's neither in LD_REGS nor in NO_LD_REGS but has some subregs that are in LD_REGS. Use the MSB (REG:QI 17). */ - if (REGNO (dest) < 16 - && REGNO (dest) + GET_MODE_SIZE (mode) > 16) + if (REGNO (dest) < REG_16 + && REGNO (dest) + GET_MODE_SIZE (mode) > REG_16) { clobber_reg = all_regs_rtx[REGNO (dest) + n_bytes - 1]; } @@ -14093,7 +14095,7 @@ avr_conditional_register_usage (void) - R0-R15 are not available in Tiny Core devices - R16 and R17 are fixed registers. */ - for (size_t i = 0; i <= 17; i++) + for (size_t i = REG_0; i <= REG_17; i++) { fixed_regs[i] = 1; call_used_regs[i] = 1; @@ -14103,7 +14105,7 @@ avr_conditional_register_usage (void) - R18, R19, R20 and R21 are the callee saved registers in Tiny Core devices */ - for (size_t i = 18; i <= LAST_CALLEE_SAVED_REG; i++) + for (size_t i = REG_18; i <= LAST_CALLEE_SAVED_REG; i++) { call_used_regs[i] = 0; } @@ -15180,9 +15182,9 @@ avr_map_decompose (unsigned int f, const avr_map_op_t *g, bool val_const_p) fake values. Mimic effect of reloading xop[3]: Unused operands are mapped to 0 and used operands are reloaded to xop[0]. */ - xop[0] = all_regs_rtx[24]; + xop[0] = all_regs_rtx[REG_24]; xop[1] = gen_int_mode (f_ginv.map, SImode); - xop[2] = all_regs_rtx[25]; + xop[2] = all_regs_rtx[REG_25]; xop[3] = val_used_p ? xop[0] : const0_rtx; avr_out_insert_bits (xop, &f_ginv.cost); diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md index 8f6bc288515..028f9f1254d 100644 --- a/gcc/config/avr/avr.md +++ b/gcc/config/avr/avr.md @@ -51,22 +51,33 @@ ;; ~ Output 'r' if not AVR_HAVE_JMP_CALL. ;; ! Output 'e' if AVR_HAVE_EIJMP_EICALL. +;; Used in avr.cc to avoid magic numbers for register numbers. +(define_constants + [(REG_0 0) (REG_1 1) (REG_2 2) + (REG_8 8) (REG_9 9) (REG_10 10) (REG_11 11) + (REG_12 12) (REG_13 13) (REG_14 14) (REG_15 15) + (REG_16 16) (REG_17 17) (REG_18 18) (REG_19 19) + (REG_20 20) (REG_21 21) (REG_22 22) (REG_23 23) + (REG_24 24) (REG_25 25) (REG_26 26) (REG_27 27) + (REG_28 28) (REG_29 29) (REG_30 30) (REG_31 31) + (REG_32 32) (REG_36 36) + ]) (define_constants - [(REG_X 26) - (REG_Y 28) - (REG_Z 30) - (REG_W 24) - (REG_SP 32) - (REG_CC 36) - (LPM_REGNO 0) ; implicit target register of LPM - (TMP_REGNO 0) ; temporary register r0 - (ZERO_REGNO 1) ; zero register r1 + [(REG_X REG_26) + (REG_Y REG_28) + (REG_Z REG_30) + (REG_W REG_24) + (REG_SP REG_32) + (REG_CC REG_36) + (LPM_REGNO REG_0) ; implicit target register of LPM + (TMP_REGNO REG_0) ; temporary register r0 + (ZERO_REGNO REG_1) ; zero register r1 ]) (define_constants - [(TMP_REGNO_TINY 16) ; r16 is temp register for AVR_TINY - (ZERO_REGNO_TINY 17) ; r17 is zero register for AVR_TINY + [(TMP_REGNO_TINY REG_16) ; r16 is temp register for AVR_TINY + (ZERO_REGNO_TINY REG_17) ; r17 is zero register for AVR_TINY ]) (define_c_enum "unspec"