[V2,10/11] Add support for -mcpu=future

Message ID	Zy5s6Vb5t2hTNog9@cowardly-lion.the-meissners.org
State	New
Headers	show Return-Path: <gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org> DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B6E683858D20 Date: Fri, 8 Nov 2024 14:56:25 -0500 From: Michael Meissner <meissner@linux.ibm.com> To: Michael Meissner <meissner@linux.ibm.com>, gcc-patches@gcc.gnu.org, Segher Boessenkool <segher@kernel.crashing.org>, Peter Bergner <bergner@linux.ibm.com> Subject: [PATCH V2 10/11] Add support for -mcpu=future Message-ID: <Zy5s6Vb5t2hTNog9@cowardly-lion.the-meissners.org> Mail-Followup-To: Michael Meissner <meissner@linux.ibm.com>, gcc-patches@gcc.gnu.org, Segher Boessenkool <segher@kernel.crashing.org>, Peter Bergner <bergner@linux.ibm.com> References: <Zy5l0UzaqaiB0STx@cowardly-lion.the-meissners.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <Zy5l0UzaqaiB0STx@cowardly-lion.the-meissners.org> Precedence: list Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org
Series	Separate PowerPC archiecture bits from ISA flags that use command line options \| expand [V2,0/11] Separate PowerPC archiecture bits from ISA flags that use command line options [V2,1/11] Add rs6000 architecture masks. [V2,2/11] Use architecture flags for defining _ARCH_PWR macros. [V2,3/11] Do not allow -mvsx to boost processor to power7. [V2,4/11] Change TARGET_POPCNTB to TARGET_POWER5 [V2,5/11] Change TARGET_FPRND to TARGET_POWER5X [V2,7/11] Change TARGET_POPCNTD to TARGET_POWER7 [V2,8/11] Change TARGET_MODULO to TARGET_POWER9 [V2,9/11] Update tests to work with architecture flags changes. [V2,10/11] Add support for -mcpu=future [V2,11/11] Add -mcpu=future tuning support.

diff --git a/gcc/config.gcc b/gcc/config.gcc index fd848228722..d552d01b439 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -539,7 +539,7 @@ powerpc*-*-*) extra_headers="${extra_headers} ppu_intrinsics.h spu2vmx.h vec_types.h si2vmx.h" extra_headers="${extra_headers} amo.h" case x$with_cpu in - xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower1[01]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500) + xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower1[01]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500|xfuture) cpu_is_64bit=yes ;; esac @@ -5647,7 +5647,7 @@ case "${target}" in tm_defines="${tm_defines} CONFIG_PPC405CR" eval "with_$which=405" ;; - "" | common | native \ + "" | common | native | future \ | power[3456789] | power1[01] | power5+ | power6x \ | powerpc | powerpc64 | powerpc64le \ | rs64 \ diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h index 41037b3852d..570ddcc451d 100644 --- a/gcc/config/rs6000/aix71.h +++ b/gcc/config/rs6000/aix71.h @@ -79,6 +79,7 @@ do { \ #undef ASM_CPU_SPEC #define ASM_CPU_SPEC \ "%{mcpu=native: %(asm_cpu_native); \ + mcpu=future: -mfuture; \ mcpu=power11: -mpwr11; \ mcpu=power10: -mpwr10; \ mcpu=power9: -mpwr9; \ diff --git a/gcc/config/rs6000/aix72.h b/gcc/config/rs6000/aix72.h index fe59f8319b4..242ca94bd06 100644 --- a/gcc/config/rs6000/aix72.h +++ b/gcc/config/rs6000/aix72.h @@ -79,6 +79,7 @@ do { \ #undef ASM_CPU_SPEC #define ASM_CPU_SPEC \ "%{mcpu=native: %(asm_cpu_native); \ + mcpu=future: -mfuture; \ mcpu=power11: -mpwr11; \ mcpu=power10: -mpwr10; \ mcpu=power9: -mpwr9; \ diff --git a/gcc/config/rs6000/aix73.h b/gcc/config/rs6000/aix73.h index 1318b0b3662..2bd6b4bb3c4 100644 --- a/gcc/config/rs6000/aix73.h +++ b/gcc/config/rs6000/aix73.h @@ -79,6 +79,7 @@ do { \ #undef ASM_CPU_SPEC #define ASM_CPU_SPEC \ "%{mcpu=native: %(asm_cpu_native); \ + mcpu=future: -mfuture; \ mcpu=power11: -mpwr11; \ mcpu=power10: -mpwr10; \ mcpu=power9: -mpwr9; \ diff --git a/gcc/config/rs6000/driver-rs6000.cc b/gcc/config/rs6000/driver-rs6000.cc index f4900724b98..c47e8b70c93 100644 --- a/gcc/config/rs6000/driver-rs6000.cc +++ b/gcc/config/rs6000/driver-rs6000.cc @@ -452,6 +452,7 @@ static const struct asm_name asm_names[] = { { "power9", "-mpwr9" }, { "power10", "-mpwr10" }, { "power11", "-mpwr11" }, + { "future", "-mfuture" }, { "powerpc", "-mppc" }, { "rs64", "-mppc" }, { "603", "-m603" }, @@ -481,6 +482,7 @@ static const struct asm_name asm_names[] = { { "power9", "-mpower9" }, { "power10", "-mpower10" }, { "power11", "-mpower11" }, + { "future", "-mfuture" }, { "a2", "-ma2" }, { "powerpc", "-mppc" }, { "powerpc64", "-mppc64" }, diff --git a/gcc/config/rs6000/rs6000-arch.def b/gcc/config/rs6000/rs6000-arch.def index e5b6e958133..d103c57867a 100644 --- a/gcc/config/rs6000/rs6000-arch.def +++ b/gcc/config/rs6000/rs6000-arch.def @@ -46,3 +46,4 @@ ARCH_EXPAND(POWER8, "power8") ARCH_EXPAND(POWER9, "power9") ARCH_EXPAND(POWER10, "power10") ARCH_EXPAND(POWER11, "power11") +ARCH_EXPAND(FUTURE, "future") diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc index c8f33289fa3..82826f96a8e 100644 --- a/gcc/config/rs6000/rs6000-c.cc +++ b/gcc/config/rs6000/rs6000-c.cc @@ -440,6 +440,8 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags, rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR10"); if ((arch_flags & ARCH_MASK_POWER11) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR11"); + if ((arch_flags & ARCH_MASK_FUTURE) != 0) + rs6000_define_or_undefine_macro (define_p, "_ARCH_FUTURE"); if ((flags & OPTION_MASK_SOFT_FLOAT) != 0) rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT"); if ((flags & OPTION_MASK_RECIP_PRECISION) != 0) diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index a3568898b0b..e73d9ef51f8 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -86,6 +86,8 @@ #define POWER11_MASKS_SERVER ISA_3_1_MASKS_SERVER +#define FUTURE_MASKS_SERVER POWER11_MASKS_SERVER + /* Flags that need to be turned off if -mno-vsx. */ #define OTHER_VSX_VECTOR_MASKS (OPTION_MASK_EFFICIENT_UNALIGNED_VSX \ | OPTION_MASK_FLOAT128_KEYWORD \ @@ -249,6 +251,7 @@ RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 | ISA_3_0_MASKS_SERVER | OPTION_MASK_HTM) RS6000_CPU ("power10", PROCESSOR_POWER10, MASK_POWERPC64 | ISA_3_1_MASKS_SERVER) RS6000_CPU ("power11", PROCESSOR_POWER11, MASK_POWERPC64 | POWER11_MASKS_SERVER) +RS6000_CPU ("future", PROCESSOR_FUTURE, MASK_POWERPC64 | FUTURE_MASKS_SERVER) RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0) RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64) diff --git a/gcc/config/rs6000/rs6000-opts.h b/gcc/config/rs6000/rs6000-opts.h index 88e357835a5..c25ddf92858 100644 --- a/gcc/config/rs6000/rs6000-opts.h +++ b/gcc/config/rs6000/rs6000-opts.h @@ -63,6 +63,7 @@ enum processor_type PROCESSOR_POWER9, PROCESSOR_POWER10, PROCESSOR_POWER11, + PROCESSOR_FUTURE, PROCESSOR_RS64A, PROCESSOR_MPCCORE, diff --git a/gcc/config/rs6000/rs6000-tables.opt b/gcc/config/rs6000/rs6000-tables.opt index a5649fef1ec..fc187c641f8 100644 --- a/gcc/config/rs6000/rs6000-tables.opt +++ b/gcc/config/rs6000/rs6000-tables.opt @@ -189,14 +189,17 @@ EnumValue Enum(rs6000_cpu_opt_value) String(power11) Value(53) EnumValue -Enum(rs6000_cpu_opt_value) String(powerpc) Value(54) +Enum(rs6000_cpu_opt_value) String(future) Value(54) EnumValue -Enum(rs6000_cpu_opt_value) String(powerpc64) Value(55) +Enum(rs6000_cpu_opt_value) String(powerpc) Value(55) EnumValue -Enum(rs6000_cpu_opt_value) String(powerpc64le) Value(56) +Enum(rs6000_cpu_opt_value) String(powerpc64) Value(56) EnumValue -Enum(rs6000_cpu_opt_value) String(rs64) Value(57) +Enum(rs6000_cpu_opt_value) String(powerpc64le) Value(57) + +EnumValue +Enum(rs6000_cpu_opt_value) String(rs64) Value(58) diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 7d20e757c7c..aa67e7256bb 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -1068,7 +1068,7 @@ struct processor_costs power9_cost = { COSTS_N_INSNS (3), /* SF->DF convert */ }; -/* Instruction costs on Power10/Power11 processors. */ +/* Instruction costs on Power10/Power11/future processors. */ static const struct processor_costs power10_cost = { COSTS_N_INSNS (2), /* mulsi */ @@ -1837,10 +1837,15 @@ get_arch_flags (int cpu_index) const HOST_WIDE_INT ARCH_COMBO_POWER9 = ARCH_MASK_POWER9 | ARCH_COMBO_POWER8; const HOST_WIDE_INT ARCH_COMBO_POWER10 = ARCH_MASK_POWER10 | ARCH_COMBO_POWER9; const HOST_WIDE_INT ARCH_COMBO_POWER11 = ARCH_MASK_POWER11 | ARCH_COMBO_POWER10; + const HOST_WIDE_INT ARCH_COMBO_FUTURE = ARCH_MASK_FUTURE | ARCH_COMBO_POWER11; if (cpu_index >= 0) switch (processor_target_table[cpu_index].processor) { + case PROCESSOR_FUTURE: + ret = ARCH_COMBO_FUTURE; + break; + case PROCESSOR_POWER11: ret = ARCH_COMBO_POWER11; break; @@ -4428,7 +4433,8 @@ rs6000_option_override_internal (bool global_init_p) if (!(rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION)) { if (rs6000_tune == PROCESSOR_POWER10 - || rs6000_tune == PROCESSOR_POWER11) + || rs6000_tune == PROCESSOR_POWER11 + || rs6000_tune == PROCESSOR_FUTURE) rs6000_isa_flags |= OPTION_MASK_P10_FUSION; else rs6000_isa_flags &= ~OPTION_MASK_P10_FUSION; @@ -4459,6 +4465,7 @@ rs6000_option_override_internal (bool global_init_p) && rs6000_tune != PROCESSOR_POWER9 && rs6000_tune != PROCESSOR_POWER10 && rs6000_tune != PROCESSOR_POWER11 + && rs6000_tune != PROCESSOR_FUTURE && rs6000_tune != PROCESSOR_PPCA2 && rs6000_tune != PROCESSOR_CELL && rs6000_tune != PROCESSOR_PPC476); @@ -4474,6 +4481,7 @@ rs6000_option_override_internal (bool global_init_p) || rs6000_tune == PROCESSOR_POWER9 || rs6000_tune == PROCESSOR_POWER10 || rs6000_tune == PROCESSOR_POWER11 + || rs6000_tune == PROCESSOR_FUTURE || rs6000_tune == PROCESSOR_PPCE500MC || rs6000_tune == PROCESSOR_PPCE500MC64 || rs6000_tune == PROCESSOR_PPCE5500 @@ -4774,6 +4782,7 @@ rs6000_option_override_internal (bool global_init_p) case PROCESSOR_POWER10: case PROCESSOR_POWER11: + case PROCESSOR_FUTURE: rs6000_cost = &power10_cost; break; @@ -5947,6 +5956,8 @@ rs6000_machine_from_flags (void) flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT | OPTION_MASK_ISEL | OPTION_MASK_ALTIVEC); + if ((arch_flags & ARCH_MASK_FUTURE) != 0) + return "future"; if ((arch_flags & ARCH_MASK_POWER11) != 0) return "power11"; if ((arch_flags & ARCH_MASK_POWER10) != 0) @@ -10198,6 +10209,7 @@ rs6000_reassociation_width (unsigned int opc ATTRIBUTE_UNUSED, case PROCESSOR_POWER9: case PROCESSOR_POWER10: case PROCESSOR_POWER11: + case PROCESSOR_FUTURE: if (DECIMAL_FLOAT_MODE_P (mode)) return 1; if (VECTOR_MODE_P (mode)) @@ -18285,7 +18297,8 @@ rs6000_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost, /* Separate a load from a narrower, dependent store. */ if ((rs6000_sched_groups || rs6000_tune == PROCESSOR_POWER9 || rs6000_tune == PROCESSOR_POWER10 - || rs6000_tune == PROCESSOR_POWER11) + || rs6000_tune == PROCESSOR_POWER11 + || rs6000_tune == PROCESSOR_FUTURE) && GET_CODE (PATTERN (insn)) == SET && GET_CODE (PATTERN (dep_insn)) == SET && MEM_P (XEXP (PATTERN (insn), 1)) @@ -18325,6 +18338,7 @@ rs6000_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost, || rs6000_tune == PROCESSOR_POWER9 || rs6000_tune == PROCESSOR_POWER10 || rs6000_tune == PROCESSOR_POWER11 + || rs6000_tune == PROCESSOR_FUTURE || rs6000_tune == PROCESSOR_CELL) && recog_memoized (dep_insn) && (INSN_CODE (dep_insn) >= 0)) @@ -18900,6 +18914,7 @@ rs6000_issue_rate (void) return 6; case PROCESSOR_POWER10: case PROCESSOR_POWER11: + case PROCESSOR_FUTURE: return 8; default: return 1; @@ -19615,10 +19630,11 @@ rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose, if (rs6000_tune == PROCESSOR_POWER6) load_store_pendulum = 0; - /* Do Power10/Power11 dependent reordering. */ + /* Do Power10/Power11/future dependent reordering. */ if (last_scheduled_insn && (rs6000_tune == PROCESSOR_POWER10 - || rs6000_tune == PROCESSOR_POWER11)) + || rs6000_tune == PROCESSOR_POWER11 + || rs6000_tune == PROCESSOR_FUTURE)) power10_sched_reorder (ready, n_ready - 1); return rs6000_issue_rate (); @@ -19642,10 +19658,11 @@ rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx_insn **ready, && recog_memoized (last_scheduled_insn) >= 0) return power9_sched_reorder2 (ready, *pn_ready - 1); - /* Do Power10/Power11 dependent reordering. */ + /* Do Power10/Power11/future dependent reordering. */ if (last_scheduled_insn && (rs6000_tune == PROCESSOR_POWER10 - || rs6000_tune == PROCESSOR_POWER11)) + || rs6000_tune == PROCESSOR_POWER11 + || rs6000_tune == PROCESSOR_FUTURE)) return power10_sched_reorder (ready, *pn_ready - 1); return cached_can_issue_more; @@ -22863,7 +22880,8 @@ rs6000_register_move_cost (machine_mode mode, out to be a nop. */ if (rs6000_tune == PROCESSOR_POWER9 || rs6000_tune == PROCESSOR_POWER10 - || rs6000_tune == PROCESSOR_POWER11) + || rs6000_tune == PROCESSOR_POWER11 + || rs6000_tune == PROCESSOR_FUTURE) ret = 3 * hard_regno_nregs (FIRST_GPR_REGNO, mode); else ret = 4 * hard_regno_nregs (FIRST_GPR_REGNO, mode); diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 89ca1bad80f..8cfd9faf77d 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -101,6 +101,7 @@ you make changes here, make them also there. */ #define ASM_CPU_SPEC \ "%{mcpu=native: %(asm_cpu_native); \ + mcpu=future: -mfuture; \ mcpu=power11: -mpower11; \ mcpu=power10: -mpower10; \ mcpu=power9: -mpower9; \ @@ -531,6 +532,7 @@ extern int rs6000_vector_align[]; #define TARGET_POWER9 ((rs6000_arch_flags & ARCH_MASK_POWER9) != 0) #define TARGET_POWER10 ((rs6000_arch_flags & ARCH_MASK_POWER10) != 0) #define TARGET_POWER11 ((rs6000_arch_flags & ARCH_MASK_POWER11) != 0) +#define TARGET_FUTURE ((rs6000_arch_flags & ARCH_MASK_FUTURE) != 0) /* In the past we represented power8, power10 as an ISA bit and used internal switches the user was not supposed to use for -mpower8-internal and diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index fc0d454e9a4..6642a471796 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -364,7 +364,7 @@ (define_attr "cpu" ppc750,ppc7400,ppc7450, ppc403,ppc405,ppc440,ppc476, ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500, - power4,power5,power6,power7,power8,power9,power10,power11, + power4,power5,power6,power7,power8,power9,power10,power11,future, rs64a,mpccore,cell,ppca2,titan" (const (symbol_ref "(enum attr_cpu) rs6000_tune")))

[V2,10/11] Add support for -mcpu=future

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