diff mbox series

PR 99293: Optimize splat of a V2DF/V2DI extract with constant element

Message ID Zuj7dJ4iTdswAZ-b@cowardly-lion.the-meissners.org
State New
Headers show
Series PR 99293: Optimize splat of a V2DF/V2DI extract with constant element | expand

Commit Message

Michael Meissner Sept. 17, 2024, 3:45 a.m. UTC 
This is an old patch that I first wrote in 2021, and in the press of other
work, the patch got lost.

We had optimizations for splat of a vector extract for the other vector
types, but we missed having one for V2DI and V2DF.  This patch adds a
combiner insn to do this optimization.

In looking at the source, we had similar optimizations for V4SI and V4SF
extract and splats, but we missed doing V2DI/V2DF.

Without the patch for the code:

	vector long long splat_dup_l_0 (vector long long v)
	{
	  return __builtin_vec_splats (__builtin_vec_extract (v, 0));
	}

the compiler generates (on a little endian power9):

	splat_dup_l_0:
		mfvsrld 9,34
	        mtvsrdd 34,9,9
		blr

Now it generates:

	splat_dup_l_0:
		xxpermdi 34,34,34,3
	        blr

I have built compilers with this patch on little endian and big endian PowerPC
servers, and there was no regression in the code.  Can I apply this patch to
the master trunk for GCC 15?

2024-09-16  Michael Meissner  <meissner@linux.ibm.com>

gcc/

	* config/rs6000/vsx.md (vsx_splat_extract_<mode>): New insn.

gcc/testsuite/

	* gcc.target/powerpc/builtins-1.c: Adjust insn count.
	* gcc.target/powerpc/pr99293.c: New test.
---
 gcc/config/rs6000/vsx.md                      | 18 +++++++++++++++
 gcc/testsuite/gcc.target/powerpc/builtins-1.c |  2 +-
 gcc/testsuite/gcc.target/powerpc/pr99293.c    | 22 +++++++++++++++++++
 3 files changed, 41 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/powerpc/pr99293.c

Comments

Michael Meissner Sept. 27, 2024, 4:44 p.m. UTC | #1 
This patch seems to have been over looked.

https://gcc.gnu.org/pipermail/gcc-patches/2024-September/663101.html

I ran a set of spec 2017 benchmarks with this patch applied and compared it to
a run without the patch applied.  There were no regressions, but 3 benchmarks
had slight improvement in runtime with this patch applied on a power10 system:

    505.mcf_r         101.67%
    520.omnetpp_r     103.35%
    523.xalancbmk_r   101.15%
Michael Meissner Oct. 7, 2024, 7:52 p.m. UTC | #2 
This patch seems to have been over looked.

https://gcc.gnu.org/pipermail/gcc-patches/2024-September/663101.html
Michael Meissner Oct. 24, 2024, 10:39 p.m. UTC | #3 
This patch seems to have been over looked.

https://gcc.gnu.org/pipermail/gcc-patches/2024-September/663101.html

I ran a set of spec 2017 benchmarks with this patch applied and compared it to
a run without the patch applied.  There were no regressions, but 3 benchmarks
had slight improvement in runtime with this patch applied on a power10 system:

    505.mcf_r         101.67%
    520.omnetpp_r     103.35%
    523.xalancbmk_r   101.15%
diff mbox series

Patch

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index b2fc39acf4e..73f20a86e56 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4796,6 +4796,24 @@  (define_insn "vsx_splat_<mode>_mem"
   "lxvdsx %x0,%y1"
   [(set_attr "type" "vecload")])
 
+;; Optimize SPLAT of an extract from a V2DF/V2DI vector with a constant element
+(define_insn "*vsx_splat_extract_<mode>"
+  [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wa")
+	(vec_duplicate:VSX_D
+	 (vec_select:<VEC_base>
+	  (match_operand:VSX_D 1 "vsx_register_operand" "wa")
+	  (parallel [(match_operand 2 "const_0_to_1_operand" "n")]))))]
+  "VECTOR_MEM_VSX_P (<MODE>mode)"
+{
+  int which_word = INTVAL (operands[2]);
+  if (!BYTES_BIG_ENDIAN)
+    which_word = 1 - which_word;
+
+  operands[3] = GEN_INT (which_word ? 3 : 0);
+  return "xxpermdi %x0,%x1,%x1,%3";
+}
+  [(set_attr "type" "vecperm")])
+
 ;; V4SI splat support
 (define_insn "vsx_splat_v4si"
   [(set (match_operand:V4SI 0 "vsx_register_operand" "=wa,wa")
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-1.c b/gcc/testsuite/gcc.target/powerpc/builtins-1.c
index 8410a5fd431..4e7e5384675 100644
--- a/gcc/testsuite/gcc.target/powerpc/builtins-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-1.c
@@ -1035,4 +1035,4 @@  foo156 (vector unsigned short usa)
 /* { dg-final { scan-assembler-times {\mvmrglb\M} 3 } } */
 /* { dg-final { scan-assembler-times {\mvmrgew\M} 4 } } */
 /* { dg-final { scan-assembler-times {\mvsplth|xxsplth\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mxxpermdi\M} 44 } } */
+/* { dg-final { scan-assembler-times {\mxxpermdi\M} 42 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr99293.c b/gcc/testsuite/gcc.target/powerpc/pr99293.c
new file mode 100644
index 00000000000..20adc1f27f6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr99293.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mvsx" } */
+
+/* Test for PR 99263, which wants to do:
+	__builtin_vec_splats (__builtin_vec_extract (v, n))
+
+   where v is a V2DF or V2DI vector and n is either 0 or 1.  Previously the
+   compiler would do a direct move to the GPR registers to select the item and a
+   direct move from the GPR registers to do the splat.  */
+
+vector long long splat_dup_l_0 (vector long long v)
+{
+  return __builtin_vec_splats (__builtin_vec_extract (v, 0));
+}
+
+vector long long splat_dup_l_1 (vector long long v)
+{
+  return __builtin_vec_splats (__builtin_vec_extract (v, 1));
+}
+
+/* { dg-final { scan-assembler-times "xxpermdi" 2 } } */