diff mbox series

[6/9] Change TARGET_CMPB to TARGET_POWER6

Message ID Zqx5rp35UrzEgDfh@cowardly-lion.the-meissners.org
State New
Headers show
Series Adding PowerPC architecture flags in addition to ISA flags | expand

Commit Message

Michael Meissner Aug. 2, 2024, 6:16 a.m. UTC 
As part of the architecture flags patches, this patch changes the use of
TARGET_FPRND to TARGET_POWER6.  The CMPB instruction was added in power6 (ISA
2.05).

I have built both big endian and little endian bootstrap compilers and there
were no regressions.

In addition, I constructed a test case that used every archiecture define (like
_ARCH_PWR4, etc.) and I also looked at the .machine directive generated.  I ran
this test for all supported combinations of -mcpu, big/little endian, and 32/64
bit support.  Every single instance generated exactly the same code with the
patches installed compared to the compiler before installing the patches.

Can I install this patch on the GCC 15 trunk?

2024-08-01  Michael Meissner  <meissner@linux.ibm.com>

	* config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Use
	TARGET_POWER6 instead of TARGET_CMPB.
	* config/rs6000/rs6000.h (TARGET_FCFID): Merge tests for popcntb, cmpb,
	and popcntd into a single test for TARGET_POWER5.
	(TARGET_LFIWAX): Use TARGET_POWER6 instead of TARGET_CMPB.
	* config/rs6000/rs6000.md (enabled attribute): Likewise.
	(parity<mode>2_cmp): Likewise.
	(cmpb): Likewise.
	(copysign<mode>3): Likewise.
	(copysign<mode>3_fcpsgn): Likewise.
	(cmpstrnsi): Likewise.
	(cmpstrsi): Likewise.
---
 gcc/config/rs6000/rs6000-builtin.cc |  4 ++--
 gcc/config/rs6000/rs6000.h          |  6 ++----
 gcc/config/rs6000/rs6000.md         | 16 ++++++++--------
 3 files changed, 12 insertions(+), 14 deletions(-)
diff mbox series

Patch

diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc
index ba2eba15378..ddf744cd988 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -157,9 +157,9 @@  rs6000_builtin_is_supported (enum rs6000_gen_builtins fncode)
     case ENB_P5:
       return TARGET_POWER5;
     case ENB_P6:
-      return TARGET_CMPB;
+      return TARGET_POWER6;
     case ENB_P6_64:
-      return TARGET_CMPB && TARGET_POWERPC64;
+      return TARGET_POWER6 && TARGET_POWERPC64;
     case ENB_P7:
       return TARGET_POPCNTD;
     case ENB_P7_64:
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 4ad0fca1d60..924ca682172 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -448,13 +448,11 @@  extern int rs6000_vector_align[];
    Enable 32-bit fcfid's on any of the switches for newer ISA machines.  */
 #define TARGET_FCFID	(TARGET_POWERPC64				\
 			 || TARGET_PPC_GPOPT	/* 970/power4 */	\
-			 || TARGET_POPCNTB	/* ISA 2.02 */		\
-			 || TARGET_CMPB		/* ISA 2.05 */		\
-			 || TARGET_POPCNTD)	/* ISA 2.06 */
+			 || TARGET_POWER5)	/* ISA 2.02 and above */ \
 
 #define TARGET_FCTIDZ	TARGET_FCFID
 #define TARGET_STFIWX	TARGET_PPC_GFXOPT
-#define TARGET_LFIWAX	TARGET_CMPB
+#define TARGET_LFIWAX	TARGET_POWER6
 #define TARGET_LFIWZX	TARGET_POPCNTD
 #define TARGET_FCFIDS	TARGET_POPCNTD
 #define TARGET_FCFIDU	TARGET_POPCNTD
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 6555b50dc98..dd3bfcc6a3a 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -369,7 +369,7 @@  (define_attr "enabled" ""
      (const_int 1)
 
      (and (eq_attr "isa" "p6")
-	  (match_test "TARGET_CMPB"))
+	  (match_test "TARGET_POWER6"))
      (const_int 1)
 
      (and (eq_attr "isa" "p7")
@@ -2509,7 +2509,7 @@  (define_expand "parity<mode>2"
 (define_insn "parity<mode>2_cmpb"
   [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
 	(unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] UNSPEC_PARITY))]
-  "TARGET_CMPB"
+  "TARGET_POWER6"
   "prty<wd> %0,%1"
   [(set_attr "type" "popcnt")])
 
@@ -2562,7 +2562,7 @@  (define_insn "cmpb<mode>3"
   [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
 	(unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")
 		     (match_operand:GPR 2 "gpc_reg_operand" "r")] UNSPEC_CMPB))]
-  "TARGET_CMPB"
+  "TARGET_POWER6"
   "cmpb %0,%1,%2"
   [(set_attr "type" "cmp")])
 
@@ -5366,7 +5366,7 @@  (define_expand "copysign<mode>3"
    && ((TARGET_PPC_GFXOPT
         && !HONOR_NANS (<MODE>mode)
         && !HONOR_SIGNED_ZEROS (<MODE>mode))
-       || TARGET_CMPB
+       || TARGET_POWER6
        || VECTOR_UNIT_VSX_P (<MODE>mode))"
 {
   /* Middle-end canonicalizes -fabs (x) to copysign (x, -1),
@@ -5387,7 +5387,7 @@  (define_expand "copysign<mode>3"
   if (!gpc_reg_operand (operands[2], <MODE>mode))
     operands[2] = copy_to_mode_reg (<MODE>mode, operands[2]);
 
-  if (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))
+  if (TARGET_POWER6 || VECTOR_UNIT_VSX_P (<MODE>mode))
     {
       emit_insn (gen_copysign<mode>3_fcpsgn (operands[0], operands[1],
 					     operands[2]));
@@ -5403,7 +5403,7 @@  (define_insn "copysign<mode>3_fcpsgn"
   [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
 	(copysign:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "d,wa") 
 		       (match_operand:SFDF 2 "gpc_reg_operand" "d,wa")))]
-  "TARGET_HARD_FLOAT && (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))"
+  "TARGET_HARD_FLOAT && (TARGET_POWER6 || VECTOR_UNIT_VSX_P (<MODE>mode))"
   "@
    fcpsgn %0,%2,%1
    xscpsgndp %x0,%x2,%x1"
@@ -10087,7 +10087,7 @@  (define_expand "cmpstrnsi"
                            (match_operand:BLK 2)))
 	      (use (match_operand:SI 3))
 	      (use (match_operand:SI 4))])]
-  "TARGET_CMPB && (BYTES_BIG_ENDIAN || TARGET_LDBRX)"
+  "TARGET_POWER6 && (BYTES_BIG_ENDIAN || TARGET_LDBRX)"
 {
   if (optimize_insn_for_size_p ())
     FAIL;
@@ -10109,7 +10109,7 @@  (define_expand "cmpstrsi"
                (compare:SI (match_operand:BLK 1)
                            (match_operand:BLK 2)))
 	      (use (match_operand:SI 3))])]
-  "TARGET_CMPB && (BYTES_BIG_ENDIAN || TARGET_LDBRX)"
+  "TARGET_POWER6 && (BYTES_BIG_ENDIAN || TARGET_LDBRX)"
 {
   if (optimize_insn_for_size_p ())
     FAIL;