diff --git a/gcc/config/rs6000/dfp.md b/gcc/config/rs6000/dfp.md
index fa9d7dd45dd..b8189390d41 100644
--- a/gcc/config/rs6000/dfp.md
+++ b/gcc/config/rs6000/dfp.md
@@ -214,7 +214,7 @@ (define_insn "*cmp<mode>_internal1"
 (define_insn "floatdidd2"
   [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
 	(float:DD (match_operand:DI 1 "gpc_reg_operand" "d")))]
-  "TARGET_DFP && TARGET_POPCNTD"
+  "TARGET_DFP && TARGET_POWER7"
   "dcffix %0,%1"
   [(set_attr "type" "dfp")])
 
diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc
index ddf744cd988..140422170a1 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -161,9 +161,9 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins fncode)
     case ENB_P6_64:
       return TARGET_POWER6 && TARGET_POWERPC64;
     case ENB_P7:
-      return TARGET_POPCNTD;
+      return TARGET_POWER7;
     case ENB_P7_64:
-      return TARGET_POPCNTD && TARGET_POWERPC64;
+      return TARGET_POWER7 && TARGET_POWERPC64;
     case ENB_P8:
       return TARGET_POWER8;
     case ENB_P8V:
diff --git a/gcc/config/rs6000/rs6000-string.cc b/gcc/config/rs6000/rs6000-string.cc
index 55b4133b1a3..3674c4bd984 100644
--- a/gcc/config/rs6000/rs6000-string.cc
+++ b/gcc/config/rs6000/rs6000-string.cc
@@ -1948,8 +1948,8 @@ expand_block_compare_gpr(unsigned HOST_WIDE_INT bytes, unsigned int base_align,
 bool
 expand_block_compare (rtx operands[])
 {
-  /* TARGET_POPCNTD is already guarded at expand cmpmemsi.  */
-  gcc_assert (TARGET_POPCNTD);
+  /* TARGET_POWER7 is already guarded at expand cmpmemsi.  */
+  gcc_assert (TARGET_POWER7);
 
   /* For P8, this case is complicated to handle because the subtract
      with carry instructions do not generate the 64-bit carry and so
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 7d50fd97ad8..12d9b11de00 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1998,7 +1998,7 @@ rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode)
 	  if(GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD)
 	    return 1;
 
-	  if (TARGET_POPCNTD && mode == SImode)
+	  if (TARGET_POWER7 && mode == SImode)
 	    return 1;
 
 	  if (TARGET_P9_VECTOR && (mode == QImode || mode == HImode))
@@ -22476,7 +22476,7 @@ rs6000_rtx_costs (rtx x, machine_mode mode, int outer_code,
       return false;
 
     case POPCOUNT:
-      *total = COSTS_N_INSNS (TARGET_POPCNTD ? 1 : 6);
+      *total = COSTS_N_INSNS (TARGET_POWER7 ? 1 : 6);
       return false;
 
     case PARITY:
@@ -23263,7 +23263,7 @@ rs6000_emit_popcount (rtx dst, rtx src)
   rtx tmp1, tmp2;
 
   /* Use the PPC ISA 2.06 popcnt{w,d} instruction if we can.  */
-  if (TARGET_POPCNTD)
+  if (TARGET_POWER7)
     {
       if (mode == SImode)
 	emit_insn (gen_popcntdsi2 (dst, src));
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 924ca682172..b5b9c01683b 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -442,7 +442,7 @@ extern int rs6000_vector_align[];
 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size > 64)
 #define TARGET_IEEEQUAD rs6000_ieeequad
 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi
-#define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL)
+#define TARGET_LDBRX (TARGET_POWER7 || rs6000_cpu == PROCESSOR_CELL)
 
 /* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only.
    Enable 32-bit fcfid's on any of the switches for newer ISA machines.  */
@@ -453,12 +453,12 @@ extern int rs6000_vector_align[];
 #define TARGET_FCTIDZ	TARGET_FCFID
 #define TARGET_STFIWX	TARGET_PPC_GFXOPT
 #define TARGET_LFIWAX	TARGET_POWER6
-#define TARGET_LFIWZX	TARGET_POPCNTD
-#define TARGET_FCFIDS	TARGET_POPCNTD
-#define TARGET_FCFIDU	TARGET_POPCNTD
-#define TARGET_FCFIDUS	TARGET_POPCNTD
-#define TARGET_FCTIDUZ	TARGET_POPCNTD
-#define TARGET_FCTIWUZ	TARGET_POPCNTD
+#define TARGET_LFIWZX	TARGET_POWER7
+#define TARGET_FCFIDS	TARGET_POWER7
+#define TARGET_FCFIDU	TARGET_POWER7
+#define TARGET_FCFIDUS	TARGET_POWER7
+#define TARGET_FCTIDUZ	TARGET_POWER7
+#define TARGET_FCTIWUZ	TARGET_POWER7
 /* Only powerpc64 and powerpc476 support fctid.  */
 #define TARGET_FCTID	(TARGET_POWERPC64 || rs6000_cpu == PROCESSOR_PPC476)
 #define TARGET_CTZ	TARGET_MODULO
@@ -1752,7 +1752,7 @@ typedef struct rs6000_args
    zero.  The hardware instructions added in Power9 and the sequences using
    popcount return 32 or 64.  */
 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE)				\
-  (TARGET_CTZ || TARGET_POPCNTD						\
+  (TARGET_CTZ || TARGET_POWER7						\
    ? ((VALUE) = GET_MODE_BITSIZE (MODE), 2)				\
    : ((VALUE) = -1, 2))
 
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index dd3bfcc6a3a..089377e5b6a 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -373,7 +373,7 @@ (define_attr "enabled" ""
      (const_int 1)
 
      (and (eq_attr "isa" "p7")
-	  (match_test "TARGET_POPCNTD"))
+	  (match_test "TARGET_POWER7"))
      (const_int 1)
 
      (and (eq_attr "isa" "p7v")
@@ -2431,7 +2431,7 @@ (define_expand "ctz<mode>2"
   rtx tmp2 = gen_reg_rtx (<MODE>mode);
   rtx tmp3 = gen_reg_rtx (<MODE>mode);
 
-  if (TARGET_POPCNTD)
+  if (TARGET_POWER7)
     {
       emit_insn (gen_add<mode>3 (tmp1, operands[1], constm1_rtx));
       emit_insn (gen_one_cmpl<mode>2 (tmp2, operands[1]));
@@ -2492,7 +2492,7 @@ (define_insn "popcntb<mode>2"
 (define_insn "popcntd<mode>2"
   [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
 	(popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
-  "TARGET_POPCNTD"
+  "TARGET_POWER7"
   "popcnt<wd> %0,%1"
   [(set_attr "type" "popcnt")])
 
@@ -6749,7 +6749,7 @@ (define_expand "lrint<mode>si2"
   /* For those old archs in which SImode can't be hold in float registers,
      call lrint<mode>si_di to put the result in DImode then convert it via
      stack.  */
-  if (!TARGET_POPCNTD)
+  if (!TARGET_POWER7)
     {
       rtx tmp = gen_reg_rtx (DImode);
       emit_insn (gen_lrint<mode>si_di (tmp, operands[1]));
@@ -6764,7 +6764,7 @@ (define_insn "*lrint<mode>si"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=d")
 	(unspec:SI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
 		   UNSPEC_FCTIW))]
-  "TARGET_HARD_FLOAT && TARGET_POPCNTD"
+  "TARGET_HARD_FLOAT && TARGET_POWER7"
   "fctiw %0,%1"
   [(set_attr "type" "fp")])
 
@@ -6772,7 +6772,7 @@ (define_insn "lrint<mode>si_di"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
 	(unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
 		   UNSPEC_FCTIW))]
-  "TARGET_HARD_FLOAT && !TARGET_POPCNTD"
+  "TARGET_HARD_FLOAT && !TARGET_POWER7"
   "fctiw %0,%1"
   [(set_attr "type" "fp")])
 
@@ -10133,7 +10133,7 @@ (define_expand "cmpmemsi"
                            (match_operand:BLK 2)))
 	      (use (match_operand:SI 3))
 	      (use (match_operand:SI 4))])]
-  "TARGET_POPCNTD"
+  "TARGET_POWER7"
 {
   if (optimize_insn_for_size_p ())
     FAIL;
@@ -14400,7 +14400,7 @@ (define_insn "bpermd_<mode>"
   [(set (match_operand:P 0 "gpc_reg_operand" "=r")
 	(unspec:P [(match_operand:P 1 "gpc_reg_operand" "r")
 		   (match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))]
-  "TARGET_POPCNTD"
+  "TARGET_POWER7"
   "bpermd %0,%1,%2"
   [(set_attr "type" "popcnt")])
 
@@ -14778,7 +14778,7 @@ (define_insn "addg6s"
 	(unspec:SI [(match_operand:SI 1 "register_operand" "r")
 		    (match_operand:SI 2 "register_operand" "r")]
 		   UNSPEC_ADDG6S))]
-  "TARGET_POPCNTD"
+  "TARGET_POWER7"
   "addg6s %0,%1,%2"
   [(set_attr "type" "integer")])
 
@@ -14786,7 +14786,7 @@ (define_insn "cdtbcd"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(unspec:SI [(match_operand:SI 1 "register_operand" "r")]
 		   UNSPEC_CDTBCD))]
-  "TARGET_POPCNTD"
+  "TARGET_POWER7"
   "cdtbcd %0,%1"
   [(set_attr "type" "integer")])
 
@@ -14794,7 +14794,7 @@ (define_insn "cbcdtd"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(unspec:SI [(match_operand:SI 1 "register_operand" "r")]
 		   UNSPEC_CBCDTD))]
-  "TARGET_POPCNTD"
+  "TARGET_POWER7"
   "cbcdtd %0,%1"
   [(set_attr "type" "integer")])
 
@@ -14809,7 +14809,7 @@ (define_insn "div<div_extend>_<mode>"
 	(unspec:GPR [(match_operand:GPR 1 "register_operand" "r")
 		     (match_operand:GPR 2 "register_operand" "r")]
 		    UNSPEC_DIV_EXTEND))]
-  "TARGET_POPCNTD"
+  "TARGET_POWER7"
   "div<wd><div_extend> %0,%1,%2"
   [(set_attr "type" "div")
    (set_attr "size" "<bits>")])
