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Wed, 10 Jul 2024 17:34:30 GMT Received: from smtpav04.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 89EDC58054; Wed, 10 Jul 2024 17:34:28 +0000 (GMT) Received: from smtpav04.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C0EBC58045; Wed, 10 Jul 2024 17:34:27 +0000 (GMT) Received: from cowardly-lion.the-meissners.org (unknown [9.61.82.53]) by smtpav04.wdc07v.mail.ibm.com (Postfix) with ESMTPS; Wed, 10 Jul 2024 17:34:27 +0000 (GMT) Date: Wed, 10 Jul 2024 13:34:26 -0400 From: Michael Meissner To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , "Kewen.Lin" , David Edelsohn , Peter Bergner Subject: [REPOST 1/3] Add support for -mcpu=power11 Message-ID: Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , "Kewen.Lin" , David Edelsohn , Peter Bergner References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: xkn4nphPALP7AyU97VQ_W1NoPRaPpbwx X-Proofpoint-GUID: 5jPDPdmmsLlbV_3gj1WJXZVnnbFWO5Jt X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-10_12,2024-07-10_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 phishscore=0 adultscore=0 malwarescore=0 suspectscore=0 bulkscore=0 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2407100122 X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org [This is a repost of the June 4th patch] This patch adds the power11 option to the -mcpu= and -mtune= switches. This patch treats the power11 like a power10 in terms of costs and reassociation width. This patch issues a ".machine power11" to the assembly file if you use -mcpu=power11. This patch defines _ARCH_PWR11 if the user uses -mcpu=power11. This patch allows GCC to be configured with the --with-cpu=power11 and --with-tune=power11 options. This patch passes -mpwr11 to the assembler if the user uses -mcpu=power11. This patch adds support for using "power11" in the __builtin_cpu_is built-in function. 2024-07-02 Michael Meissner gcc/ * config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11. * config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=power11. * config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise. * config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise. * config/rs6000/driver-rs6000.cc (asm_names): Likewise. * config/rs6000/ppc-auxv.h (PPC_PLATFORM_POWER11): New define. * config/rs6000/rs6000-builtin.cc (cpu_is_info): Add power11. * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define _ARCH_PWR11 if -mcpu=power11. * config/rs6000/rs6000-cpus.def (ISA_POWER11_MASKS_SERVER): New define. (POWERPC_MASKS): Add power11 isa bit. (power11 cpu): Add power11 definition. * config/rs6000/rs6000-opts.h (PROCESSOR_POWER11): Add power11 processor. * config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise. * config/rs6000/rs6000-tables.opt: Regenerate. * config/rs6000/rs6000.cc (rs6000_option_override_internal): Add power11 support. (rs6000_machine_from_flags): Likewise. (rs6000_reassociation_width): Likewise. (rs6000_adjust_cost): Likewise. (rs6000_issue_rate): Likewise. (rs6000_sched_reorder): Likewise. (rs6000_sched_reorder2): Likewise. (rs6000_register_move_cost): Likewise. (rs6000_opt_masks): Likewise. * config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise. * config/rs6000/rs6000.md (cpu attribute): Add power11. * config/rs6000/rs6000.opt (-mpower11): Add internal power11 ISA flag. * doc/invoke.texi (RS/6000 and PowerPC Options): Document -mcpu=power11. --- gcc/config.gcc | 6 ++++-- gcc/config/rs6000/aix71.h | 1 + gcc/config/rs6000/aix72.h | 1 + gcc/config/rs6000/aix73.h | 1 + gcc/config/rs6000/driver-rs6000.cc | 2 ++ gcc/config/rs6000/ppc-auxv.h | 3 +-- gcc/config/rs6000/rs6000-builtin.cc | 1 + gcc/config/rs6000/rs6000-c.cc | 2 ++ gcc/config/rs6000/rs6000-cpus.def | 5 +++++ gcc/config/rs6000/rs6000-opts.h | 3 ++- gcc/config/rs6000/rs6000-string.cc | 1 + gcc/config/rs6000/rs6000-tables.opt | 3 +++ gcc/config/rs6000/rs6000.cc | 32 +++++++++++++++++++++-------- gcc/config/rs6000/rs6000.h | 1 + gcc/config/rs6000/rs6000.md | 2 +- gcc/config/rs6000/rs6000.opt | 3 +++ gcc/doc/invoke.texi | 5 +++-- 17 files changed, 56 insertions(+), 16 deletions(-) diff --git a/gcc/config.gcc b/gcc/config.gcc index bc45615741b..7c283f59e36 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -533,7 +533,9 @@ powerpc*-*-*) extra_headers="${extra_headers} ppu_intrinsics.h spu2vmx.h vec_types.h si2vmx.h" extra_headers="${extra_headers} amo.h" case x$with_cpu in - xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower10|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500) + xpowerpc64 | xdefault64 | x6[23]0 | x970 | xG5 | xpower[3456789] \ + | xpower1[01] | xpower6x | xrs64a | xcell | xa2 | xe500mc64 \ + | xe5500 | xe6500) cpu_is_64bit=yes ;; esac @@ -5641,7 +5643,7 @@ case "${target}" in eval "with_$which=405" ;; "" | common | native \ - | power[3456789] | power10 | power5+ | power6x \ + | power[3456789] | power1[01] | power5+ | power6x \ | powerpc | powerpc64 | powerpc64le \ | rs64 \ | 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \ diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h index 24bc301e37d..41037b3852d 100644 --- a/gcc/config/rs6000/aix71.h +++ b/gcc/config/rs6000/aix71.h @@ -79,6 +79,7 @@ do { \ #undef ASM_CPU_SPEC #define ASM_CPU_SPEC \ "%{mcpu=native: %(asm_cpu_native); \ + mcpu=power11: -mpwr11; \ mcpu=power10: -mpwr10; \ mcpu=power9: -mpwr9; \ mcpu=power8: -mpwr8; \ diff --git a/gcc/config/rs6000/aix72.h b/gcc/config/rs6000/aix72.h index c43974f577a..fe59f8319b4 100644 --- a/gcc/config/rs6000/aix72.h +++ b/gcc/config/rs6000/aix72.h @@ -79,6 +79,7 @@ do { \ #undef ASM_CPU_SPEC #define ASM_CPU_SPEC \ "%{mcpu=native: %(asm_cpu_native); \ + mcpu=power11: -mpwr11; \ mcpu=power10: -mpwr10; \ mcpu=power9: -mpwr9; \ mcpu=power8: -mpwr8; \ diff --git a/gcc/config/rs6000/aix73.h b/gcc/config/rs6000/aix73.h index b1572bde81f..1318b0b3662 100644 --- a/gcc/config/rs6000/aix73.h +++ b/gcc/config/rs6000/aix73.h @@ -79,6 +79,7 @@ do { \ #undef ASM_CPU_SPEC #define ASM_CPU_SPEC \ "%{mcpu=native: %(asm_cpu_native); \ + mcpu=power11: -mpwr11; \ mcpu=power10: -mpwr10; \ mcpu=power9: -mpwr9; \ mcpu=power8: -mpwr8; \ diff --git a/gcc/config/rs6000/driver-rs6000.cc b/gcc/config/rs6000/driver-rs6000.cc index 3ebbaa42622..f4900724b98 100644 --- a/gcc/config/rs6000/driver-rs6000.cc +++ b/gcc/config/rs6000/driver-rs6000.cc @@ -451,6 +451,7 @@ static const struct asm_name asm_names[] = { { "power8", "-mpwr8" }, { "power9", "-mpwr9" }, { "power10", "-mpwr10" }, + { "power11", "-mpwr11" }, { "powerpc", "-mppc" }, { "rs64", "-mppc" }, { "603", "-m603" }, @@ -479,6 +480,7 @@ static const struct asm_name asm_names[] = { { "power8", "-mpower8" }, { "power9", "-mpower9" }, { "power10", "-mpower10" }, + { "power11", "-mpower11" }, { "a2", "-ma2" }, { "powerpc", "-mppc" }, { "powerpc64", "-mppc64" }, diff --git a/gcc/config/rs6000/ppc-auxv.h b/gcc/config/rs6000/ppc-auxv.h index 364bba427d1..ed269e3b72b 100644 --- a/gcc/config/rs6000/ppc-auxv.h +++ b/gcc/config/rs6000/ppc-auxv.h @@ -47,9 +47,8 @@ #define PPC_PLATFORM_PPC476 12 #define PPC_PLATFORM_POWER8 13 #define PPC_PLATFORM_POWER9 14 - -/* This is not yet official. */ #define PPC_PLATFORM_POWER10 15 +#define PPC_PLATFORM_POWER11 16 /* AT_HWCAP bits. These must match the values defined in the Linux kernel. */ #define PPC_FEATURE_32 0x80000000 diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc index bb9da68edc7..dac449c4dd2 100644 --- a/gcc/config/rs6000/rs6000-builtin.cc +++ b/gcc/config/rs6000/rs6000-builtin.cc @@ -2496,6 +2496,7 @@ static const struct const char *cpu; unsigned int cpuid; } cpu_is_info[] = { + { "power11", PPC_PLATFORM_POWER11 }, { "power10", PPC_PLATFORM_POWER10 }, { "power9", PPC_PLATFORM_POWER9 }, { "power8", PPC_PLATFORM_POWER8 }, diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc index 6229c503bd0..68519e1397f 100644 --- a/gcc/config/rs6000/rs6000-c.cc +++ b/gcc/config/rs6000/rs6000-c.cc @@ -435,6 +435,8 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9"); if ((flags & OPTION_MASK_POWER10) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR10"); + if ((flags & OPTION_MASK_POWER11) != 0) + rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR11"); if ((flags & OPTION_MASK_SOFT_FLOAT) != 0) rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT"); if ((flags & OPTION_MASK_RECIP_PRECISION) != 0) diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index 6ee678e69c3..40fe6f4c12c 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -86,6 +86,9 @@ | OPTION_MASK_POWER10 \ | OTHER_POWER10_MASKS) +#define ISA_POWER11_MASKS_SERVER (ISA_3_1_MASKS_SERVER \ + | OPTION_MASK_POWER11) + /* Flags that need to be turned off if -mno-vsx. */ #define OTHER_VSX_VECTOR_MASKS (OPTION_MASK_EFFICIENT_UNALIGNED_VSX \ | OPTION_MASK_FLOAT128_KEYWORD \ @@ -123,6 +126,7 @@ | OPTION_MASK_FLOAT128_KEYWORD \ | OPTION_MASK_FPRND \ | OPTION_MASK_POWER10 \ + | OPTION_MASK_POWER11 \ | OPTION_MASK_P10_FUSION \ | OPTION_MASK_HTM \ | OPTION_MASK_ISEL \ @@ -256,3 +260,4 @@ RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, OPTION_MASK_PPC_GFXOPT RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER | OPTION_MASK_HTM) RS6000_CPU ("rs64", PROCESSOR_RS64A, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64) +RS6000_CPU ("power11", PROCESSOR_POWER11, MASK_POWERPC64 | ISA_POWER11_MASKS_SERVER) diff --git a/gcc/config/rs6000/rs6000-opts.h b/gcc/config/rs6000/rs6000-opts.h index 33fd0efc936..4f5af57ae1a 100644 --- a/gcc/config/rs6000/rs6000-opts.h +++ b/gcc/config/rs6000/rs6000-opts.h @@ -67,7 +67,8 @@ enum processor_type PROCESSOR_MPCCORE, PROCESSOR_CELL, PROCESSOR_PPCA2, - PROCESSOR_TITAN + PROCESSOR_TITAN, + PROCESSOR_POWER11 }; diff --git a/gcc/config/rs6000/rs6000-string.cc b/gcc/config/rs6000/rs6000-string.cc index 917f5572a6d..9c8a81172e3 100644 --- a/gcc/config/rs6000/rs6000-string.cc +++ b/gcc/config/rs6000/rs6000-string.cc @@ -964,6 +964,7 @@ expand_compare_loop (rtx operands[]) break; case PROCESSOR_POWER9: case PROCESSOR_POWER10: + case PROCESSOR_POWER11: if (bytes_is_const) max_bytes = 191; else diff --git a/gcc/config/rs6000/rs6000-tables.opt b/gcc/config/rs6000/rs6000-tables.opt index 65f46709716..7e5bb6e7658 100644 --- a/gcc/config/rs6000/rs6000-tables.opt +++ b/gcc/config/rs6000/rs6000-tables.opt @@ -197,3 +197,6 @@ Enum(rs6000_cpu_opt_value) String(powerpc64le) Value(55) EnumValue Enum(rs6000_cpu_opt_value) String(rs64) Value(56) +EnumValue +Enum(rs6000_cpu_opt_value) String(power11) Value(57) + diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 58553ff66f4..7688f5a5f04 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -1067,7 +1067,7 @@ struct processor_costs power9_cost = { COSTS_N_INSNS (3), /* SF->DF convert */ }; -/* Instruction costs on POWER10 processors. */ +/* Instruction costs on POWER10/POWER11 processors. */ static const struct processor_costs power10_cost = { COSTS_N_INSNS (2), /* mulsi */ @@ -4385,7 +4385,8 @@ rs6000_option_override_internal (bool global_init_p) generating power10 instructions. */ if (!(rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION)) { - if (rs6000_tune == PROCESSOR_POWER10) + if (rs6000_tune == PROCESSOR_POWER10 + || rs6000_tune == PROCESSOR_POWER11) rs6000_isa_flags |= OPTION_MASK_P10_FUSION; else rs6000_isa_flags &= ~OPTION_MASK_P10_FUSION; @@ -4414,6 +4415,7 @@ rs6000_option_override_internal (bool global_init_p) && rs6000_tune != PROCESSOR_POWER8 && rs6000_tune != PROCESSOR_POWER9 && rs6000_tune != PROCESSOR_POWER10 + && rs6000_tune != PROCESSOR_POWER11 && rs6000_tune != PROCESSOR_PPCA2 && rs6000_tune != PROCESSOR_CELL && rs6000_tune != PROCESSOR_PPC476); @@ -4428,6 +4430,7 @@ rs6000_option_override_internal (bool global_init_p) || rs6000_tune == PROCESSOR_POWER8 || rs6000_tune == PROCESSOR_POWER9 || rs6000_tune == PROCESSOR_POWER10 + || rs6000_tune == PROCESSOR_POWER11 || rs6000_tune == PROCESSOR_PPCE500MC || rs6000_tune == PROCESSOR_PPCE500MC64 || rs6000_tune == PROCESSOR_PPCE5500 @@ -4727,6 +4730,7 @@ rs6000_option_override_internal (bool global_init_p) break; case PROCESSOR_POWER10: + case PROCESSOR_POWER11: rs6000_cost = &power10_cost; break; @@ -5886,6 +5890,8 @@ rs6000_machine_from_flags (void) /* Disable the flags that should never influence the .machine selection. */ flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT | OPTION_MASK_ISEL); + if ((flags & (ISA_POWER11_MASKS_SERVER & ~ISA_3_1_MASKS_SERVER)) != 0) + return "power11"; if ((flags & (ISA_3_1_MASKS_SERVER & ~ISA_3_0_MASKS_SERVER)) != 0) return "power10"; if ((flags & (ISA_3_0_MASKS_SERVER & ~ISA_2_7_MASKS_SERVER)) != 0) @@ -10132,6 +10138,7 @@ rs6000_reassociation_width (unsigned int opc ATTRIBUTE_UNUSED, case PROCESSOR_POWER8: case PROCESSOR_POWER9: case PROCESSOR_POWER10: + case PROCESSOR_POWER11: if (DECIMAL_FLOAT_MODE_P (mode)) return 1; if (VECTOR_MODE_P (mode)) @@ -18213,7 +18220,8 @@ rs6000_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost, /* Separate a load from a narrower, dependent store. */ if ((rs6000_sched_groups || rs6000_tune == PROCESSOR_POWER9 - || rs6000_tune == PROCESSOR_POWER10) + || rs6000_tune == PROCESSOR_POWER10 + || rs6000_tune == PROCESSOR_POWER11) && GET_CODE (PATTERN (insn)) == SET && GET_CODE (PATTERN (dep_insn)) == SET && MEM_P (XEXP (PATTERN (insn), 1)) @@ -18252,6 +18260,7 @@ rs6000_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost, || rs6000_tune == PROCESSOR_POWER8 || rs6000_tune == PROCESSOR_POWER9 || rs6000_tune == PROCESSOR_POWER10 + || rs6000_tune == PROCESSOR_POWER11 || rs6000_tune == PROCESSOR_CELL) && recog_memoized (dep_insn) && (INSN_CODE (dep_insn) >= 0)) @@ -18826,6 +18835,7 @@ rs6000_issue_rate (void) case PROCESSOR_POWER9: return 6; case PROCESSOR_POWER10: + case PROCESSOR_POWER11: return 8; default: return 1; @@ -19541,8 +19551,10 @@ rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose, if (rs6000_tune == PROCESSOR_POWER6) load_store_pendulum = 0; - /* Do Power10 dependent reordering. */ - if (rs6000_tune == PROCESSOR_POWER10 && last_scheduled_insn) + /* Do Power10/power11 dependent reordering. */ + if (last_scheduled_insn + && (rs6000_tune == PROCESSOR_POWER10 + || rs6000_tune == PROCESSOR_POWER11)) power10_sched_reorder (ready, n_ready - 1); return rs6000_issue_rate (); @@ -19566,8 +19578,10 @@ rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx_insn **ready, && recog_memoized (last_scheduled_insn) >= 0) return power9_sched_reorder2 (ready, *pn_ready - 1); - /* Do Power10 dependent reordering. */ - if (rs6000_tune == PROCESSOR_POWER10 && last_scheduled_insn) + /* Do Power10/power11 dependent reordering. */ + if (last_scheduled_insn + && (rs6000_tune == PROCESSOR_POWER10 + || rs6000_tune == PROCESSOR_POWER11)) return power10_sched_reorder (ready, *pn_ready - 1); return cached_can_issue_more; @@ -22784,7 +22798,8 @@ rs6000_register_move_cost (machine_mode mode, allocation a move within the same class might turn out to be a nop. */ if (rs6000_tune == PROCESSOR_POWER9 - || rs6000_tune == PROCESSOR_POWER10) + || rs6000_tune == PROCESSOR_POWER10 + || rs6000_tune == PROCESSOR_POWER11) ret = 3 * hard_regno_nregs (FIRST_GPR_REGNO, mode); else ret = 4 * hard_regno_nregs (FIRST_GPR_REGNO, mode); @@ -24456,6 +24471,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] = { "float128-hardware", OPTION_MASK_FLOAT128_HW, false, true }, { "fprnd", OPTION_MASK_FPRND, false, true }, { "power10", OPTION_MASK_POWER10, false, true }, + { "power11", OPTION_MASK_POWER11, false, false }, { "hard-dfp", OPTION_MASK_DFP, false, true }, { "htm", OPTION_MASK_HTM, false, true }, { "isel", OPTION_MASK_ISEL, false, true }, diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 9211f91740a..22d19848fb2 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -106,6 +106,7 @@ you make changes here, make them also there. */ #define ASM_CPU_SPEC \ "%{mcpu=native: %(asm_cpu_native); \ + mcpu=power11: -mpower11; \ mcpu=power10: -mpower10; \ mcpu=power9: -mpower9; \ mcpu=power8|mcpu=powerpc64le: -mpower8; \ diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index a5d20594789..93a8613079f 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -351,7 +351,7 @@ (define_attr "cpu" ppc403,ppc405,ppc440,ppc476, ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500, power4,power5,power6,power7,power8,power9,power10, - rs64a,mpccore,cell,ppca2,titan" + rs64a,mpccore,cell,ppca2,titan,power11" (const (symbol_ref "(enum attr_cpu) rs6000_tune"))) ;; The ISA we implement. diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index e8ca70340df..fc00e939d88 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -585,6 +585,9 @@ Target Undocumented Var(rs6000_speculate_indirect_jumps) Init(1) Save mpower10 Target Undocumented Mask(POWER10) Var(rs6000_isa_flags) WarnRemoved +mpower11 +Target Undocumented Mask(POWER11) Var(rs6000_isa_flags) Warn(Do not use %<-mpower11>) + mprefixed Target Mask(PREFIXED) Var(rs6000_isa_flags) Generate (do not generate) prefixed memory instructions. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 68ebd79d676..469c0ffbc29 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -31488,8 +31488,9 @@ Supported values for @var{cpu_type} are @samp{401}, @samp{403}, @samp{e6500}, @samp{ec603e}, @samp{G3}, @samp{G4}, @samp{G5}, @samp{titan}, @samp{power3}, @samp{power4}, @samp{power5}, @samp{power5+}, @samp{power6}, @samp{power6x}, @samp{power7}, @samp{power8}, -@samp{power9}, @samp{power10}, @samp{powerpc}, @samp{powerpc64}, -@samp{powerpc64le}, @samp{rs64}, and @samp{native}. +@samp{power9}, @samp{power10}, @samp{power11}, +@samp{powerpc}, @samp{powerpc64}, @samp{powerpc64le}, +@samp{rs64}, and @samp{native}. @option{-mcpu=powerpc}, @option{-mcpu=powerpc64}, and @option{-mcpu=powerpc64le} specify pure 32-bit PowerPC (either