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Thu, 11 Apr 2024 05:08:10 -0400 X-MC-Unique: lDYdr16iMRaVnwVAJ7S-BA-1 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.rdu2.redhat.com [10.11.54.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 2D767801788; Thu, 11 Apr 2024 09:08:10 +0000 (UTC) Received: from tucnak.zalov.cz (unknown [10.45.224.14]) by smtp.corp.redhat.com (Postfix) with ESMTPS id A92F196B; Thu, 11 Apr 2024 09:08:09 +0000 (UTC) Received: from tucnak.zalov.cz (localhost [127.0.0.1]) by tucnak.zalov.cz (8.17.1/8.17.1) with ESMTPS id 43B97mqk3019206 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NOT); Thu, 11 Apr 2024 11:07:48 +0200 Received: (from jakub@localhost) by tucnak.zalov.cz (8.17.1/8.17.1/Submit) id 43B97lsE3019205; Thu, 11 Apr 2024 11:07:47 +0200 Date: Thu, 11 Apr 2024 11:07:47 +0200 From: Jakub Jelinek To: Uros Bizjak , Mayshao-oc Cc: gcc-patches@gcc.gnu.org Subject: [PATCH] invoke.texi: Clarify -march=lujiazui Message-ID: MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.1 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Disposition: inline X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: Jakub Jelinek Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Hi! Yesterday I was searching which exact CPUs are affected by the PR114576 wrong-code issue and went from the PTA_* bitmasks in GCC, so arrived at the goldmont, goldmont-plus, tremont and lujiazui CPUs (as -march= cases which do enable -maes and don't enable -mavx). But when double-checking that against the invoke.texi documentation, that was true for the first 3, but lujiazui said it supported AVX. I was really confused by that, until I found the https://gcc.gnu.org/pipermail/gcc-patches/2022-October/604407.html explanation. So, seems the CPUs do have AVX and F16C but -march=lujiazui doesn't enable those and even activelly attempts to filter those out from the announced CPUID features, in glibc as well as e.g. in libgcc. Thus, I think we should document what actually happens, otherwise users could assume that gcc -march=lujiazui predefines __AVX__ and __F16C__, which it doesn't. Tested on x86_64, ok for trunk? 2024-04-11 Jakub Jelinek * doc/invoke.texi (lujiazui): Clarify that while the CPUs do support AVX and F16C, -march=lujiazui actually doesn't enable those. Jakub --- gcc/doc/invoke.texi.jj 2024-04-11 09:26:01.156865894 +0200 +++ gcc/doc/invoke.texi 2024-04-11 10:47:53.457582922 +0200 @@ -34696,8 +34696,10 @@ instruction set support. @item lujiazui ZHAOXIN lujiazui CPU with x86-64, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, -SSE4.2, AVX, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT, FSGSBASE, CX16, -ABM, BMI, BMI2, F16C, FXSR, RDSEED instruction set support. +SSE4.2, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT, FSGSBASE, CX16, +ABM, BMI, BMI2, FXSR, RDSEED instruction set support. While the CPUs +do support AVX and F16C, these aren't enabled by @code{-march=lujiazui} +for performance reasons. @item yongfeng ZHAOXIN yongfeng CPU with x86-64, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1,