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Wed, 15 Mar 2017 16:04:38 +0000 Received: from VI1PR0801MB2031.eurprd08.prod.outlook.com (10.173.74.140) by VI1PR0801MB2096.eurprd08.prod.outlook.com (10.173.75.12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.947.12; Wed, 15 Mar 2017 16:04:36 +0000 Received: from VI1PR0801MB2031.eurprd08.prod.outlook.com ([10.173.74.140]) by VI1PR0801MB2031.eurprd08.prod.outlook.com ([10.173.74.140]) with mapi id 15.01.0947.020; Wed, 15 Mar 2017 16:04:35 +0000 From: Tamar Christina To: GCC Patches CC: nd , James Greenhalgh , "Richard Earnshaw" , Marcus Shawcroft Subject: [PATCH][GCC][AArch64] Fix subreg bug in scalar copysign Date: Wed, 15 Mar 2017 16:04:35 +0000 Message-ID: authentication-results: arm.com; dkim=none (message not signed) header.d=none; arm.com; dmarc=none action=none header.from=arm.com; x-ms-exchange-messagesentrepresentingtype: 1 x-ms-office365-filtering-correlation-id: 1c4392db-b8b2-42a6-8b90-08d46bbcf9a4 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: UriScan:; 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DIR:OUT; SFP:1101; SCL:1; SRVR:VI1PR0801MB2096; H:VI1PR0801MB2031.eurprd08.prod.outlook.com; FPR:; SPF:None; MLV:sfv; LANG:en; spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Mar 2017 16:04:35.0374 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0801MB2096 X-IsSubscribed: yes Hi All, This fixes a bug in the scalar version of copysign where due to a subreg were generating less than efficient code. This patch replaces return x * __builtin_copysignf (150.0f, y); which used to generate adrp x1, .LC1 mov x0, 2147483648 ins v3.d[0], x0 ldr s2, [x1, #:lo12:.LC1] bsl v3.8b, v1.8b, v2.8b fmul s0, s0, s3 ret .LC1: .word 1125515264 with mov x0, 1125515264 movi v2.2s, 0x80, lsl 24 fmov d3, x0 bit v3.8b, v1.8b, v2.8b fmul s0, s0, s3 ret removing the incorrect ins. Regression tested on aarch64-none-linux-gnu and no regressions. OK for trunk? Thanks, Tamar gcc/ 2017-03-15 Tamar Christina * config/aarch64/aarch64.md (copysignsf3): Fix mask generation. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 5adc5edb8dde9c30450b04932a37c41f84cc5ed1..435c8f50c0e521b3057c26a482315c5a82574711 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -5030,14 +5030,16 @@ (match_operand:SF 2 "register_operand")] "TARGET_FLOAT && TARGET_SIMD" { - rtx mask = gen_reg_rtx (DImode); + rtx v_bitmask = gen_reg_rtx (V2SImode); /* Juggle modes to get us in to a vector mode for BSL. */ - rtx op1 = lowpart_subreg (V2SFmode, operands[1], SFmode); + rtx op1 = lowpart_subreg (DImode, operands[1], SFmode); rtx op2 = lowpart_subreg (V2SFmode, operands[2], SFmode); rtx tmp = gen_reg_rtx (V2SFmode); - emit_move_insn (mask, GEN_INT (HOST_WIDE_INT_1U << 31)); - emit_insn (gen_aarch64_simd_bslv2sf (tmp, mask, op2, op1)); + emit_move_insn (v_bitmask, + aarch64_simd_gen_const_vector_dup (V2SImode, + HOST_WIDE_INT_M1U << 31)); + emit_insn (gen_aarch64_simd_bslv2sf (tmp, v_bitmask, op2, op1)); emit_move_insn (operands[0], lowpart_subreg (SFmode, tmp, V2SFmode)); DONE; }