From patchwork Tue May 2 15:37:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tamar Christina X-Patchwork-Id: 757694 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3wHQRW1vzXz9s4s for ; Wed, 3 May 2017 01:38:15 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="uYvJ1z8w"; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:content-type:mime-version; q=dns; s=default; b=Z0Dc6vE5Gk7cy54z+UNA4wXure5BbOt6DOJz0efvtC69uACukH cy6gt0H1bmk6VIwmn0bFWDO0YWGuzMURLd78TVW8DakgZexOzjfZop+v+aRhsAz/ tboN/rbeKWzoHcTFHKwqcEOsnp7M4V6FetqGxm5Yk9mHy9w99/OYRRVFM= DKIM-Signature: v=1; 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Tue, 02 May 2017 15:37:23 +0000 Received: from VI1PR0801MB2031.eurprd08.prod.outlook.com (10.173.74.140) by DB6PR0802MB2389.eurprd08.prod.outlook.com (10.172.250.142) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1047.13; Tue, 2 May 2017 15:37:22 +0000 Received: from VI1PR0801MB2031.eurprd08.prod.outlook.com ([10.173.74.140]) by VI1PR0801MB2031.eurprd08.prod.outlook.com ([10.173.74.140]) with mapi id 15.01.1047.023; Tue, 2 May 2017 15:37:22 +0000 From: Tamar Christina To: GCC Patches CC: nd , Kyrylo Tkachov , Richard Earnshaw , Marcus Shawcroft , James Greenhalgh , "nickc@redhat.com" , Ramana Radhakrishnan Subject: [PATCH][GCC][AArch64][ARM] Modify idiv costs for Cortex-A53 Date: Tue, 2 May 2017 15:37:21 +0000 Message-ID: authentication-results: arm.com; dkim=none (message not signed) header.d=none; arm.com; dmarc=none action=none header.from=arm.com; x-microsoft-exchange-diagnostics: 1; DB6PR0802MB2389; 7:jyJ0wLEmqVUBJi9fFYGfb845cBRltwRQ8t7QDE7grTdGW5NUPi+X999QN3FlS5iBS/jJ9kfqcuQzWDZYjHwhv1/Y88LPMRP3Yb0XmXTt/+z2KgBq6QwbN0iadQUzIBoqfupvHPrM1r+1mMQJOnPj3z+tQp2XW8QqvP56XWf1GHjeW6casQn0NcXXs5fUXfPeSnx1xmNKQpJ5FZL4STtfYgYw3WbmRmD1nO79LdfW02fCZZ0lNJGxDJ0X6gr7gcb2nauBi+RxAWj6F1qJkH/9MtvmP7jJcZuBjyU6X2MkkV7vNXd6wE7n3wA79z8DeExWfPnvUdVPcbgt5v/Me+I7dw== x-ld-processed: f34e5979-57d9-4aaa-ad4d-b122a662184d,ExtAddr x-ms-office365-filtering-correlation-id: 165ab42e-b9d0-4473-082c-08d491712012 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: UriScan:; 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DIR:OUT; SFP:1101; SCL:1; SRVR:DB6PR0802MB2389; H:VI1PR0801MB2031.eurprd08.prod.outlook.com; FPR:; SPF:None; MLV:sfv; LANG:en; spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-originalarrivaltime: 02 May 2017 15:37:21.8514 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB6PR0802MB2389 X-IsSubscribed: yes Hi All, This patch adjusts the cost model for Cortex-A53 to increase the costs of an integer division. The reason for this is that we want to always expand the division to a multiply when doing a division by constant. On the Cortex-A53 shifts are modeled to cost 1 instruction, when doing the expansion we have to perform two shifts and an addition. However because the cost model can't model things such as fusing of shifts, we have to fully cost both shifts. This leads to the cost model telling us that for the Cortex-A53 we can never do the expansion. By increasing the costs of the division by two instructions we recover the room required in the cost calculation to do the expansions. The reason for all of this is that currently the code does not produce what you'd expect, which is that division by constants are always expanded. Also it's inconsistent because unsigned division does get expanded. This all reduces the ability to do CSE when using signed modulo since that one is also expanded. Given: void f5(void) { int x = 0; while (x > -1000) { g(x % 300); x--; } } we now generate smull x0, w19, w21 asr x0, x0, 37 sub w0, w0, w19, asr 31 msub w0, w0, w20, w19 sub w19, w19, #1 bl g as opposed to sdiv w0, w19, w20 msub w0, w0, w20, w19 sub w19, w19, #1 bl g Bootstrapped and reg tested on aarch64-none-linux-gnu with no regressions. OK for trunk? Thanks, Tamar gcc/ 2017-05-02 Tamar Christina * config/arm/aarch-cost-tables.h (cortexa53_extra_cost): Increase idiv cost. diff --git a/gcc/config/arm/aarch-cost-tables.h b/gcc/config/arm/aarch-cost-tables.h index 68f84b04fe2f2cbdb66c6dd0c7add097606a7878..8cff517861aea2c249a07a07f6775c60f75fb9a0 100644 --- a/gcc/config/arm/aarch-cost-tables.h +++ b/gcc/config/arm/aarch-cost-tables.h @@ -154,7 +154,7 @@ const struct cpu_cost_table cortexa53_extra_costs = COSTS_N_INSNS (1), /* extend. */ COSTS_N_INSNS (1), /* add. */ COSTS_N_INSNS (1), /* extend_add. */ - COSTS_N_INSNS (7) /* idiv. */ + COSTS_N_INSNS (9) /* idiv. */ }, /* MULT DImode */ {