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Tue, 1 Aug 2017 10:20:35 +0000 From: Wilco Dijkstra To: GCC Patches , James Greenhalgh CC: nd Subject: Re: [PATCH][AArch64] Improve addressing of TI/TFmode Date: Tue, 1 Aug 2017 10:20:35 +0000 Message-ID: References: In-Reply-To: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Wilco.Dijkstra@arm.com; x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; HE1PR08MB2666; 7:jkPhtfdUYQLAZDCSIyDn/hwqhxA1FZ5P1jvkD9+3tODCFZpG6dZvh2iHtCGoQaddjmpZOPal//QApdnj7yZo5knlh1LlGfixySUmpbxdoo0MclslSYTLWJYw8Yju3ndULeF/PSUeHufs/sERGVLgALZLEHznP3s6g5p68CAM+8qmbcY1EbEdNVYbuI+LkfFDm7CPKh5V37q3qMvBDx6cjH3SPkuoP3lYfQLRCQcnXNZCjlxL36Mu8QzvY/WYNHwbMKt0a3MgUudq1GiSI+NCEVwkFlqUj7Hdz+HzXBLTSOSiH7DhXBfV447Cr+pODrJnrygtU6P9MfpUMHBhg56/HZTTndPm86o2i+Kxzqnhnnv59OPu3m60ZLIDKi07lDd1rs045QhOoc0q87D4Lj0KnD92tNGBle5SjXsGLBthPpQX/ssDOWy72OXZNhd3Aot15hwz6L2Y6tEfLVkxROsiBPOgeL1ozqgmGcCnaD24OWdXV/fHl+CmDBMzKSS0PhClEZqnKtBi3Q2NoHkjrAjeULlMGEEY7D+gqhweXv24kzIL6rZD7CnPNp1PbY3vR1uuk2CW6mS8P/cRNVfqmEikb7SDaicc/kjRwxRorTSnlQHs8Dg5tjFfYkufocwegV/ZPt1SfiaOjTIgY/d2inDBiP7cdDu0KEbZvlwrSdlndxjnQ+ZbRF7OFIJ9gU6rdSf3LcfcntuYbDoHmM+pY487AWhiAXkgWJ560Mtjk7KwzDg2U2PixDISbFmYSxNh0UJqSu0FLIntzq5UbUyvn2D2bxNwdbLMV3QlD/2LfiLENVQ= x-ms-office365-filtering-correlation-id: 68d7199f-048d-4046-5292-08d4d8c6f2aa x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: UriScan:; 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FPR:; SPF:None; PTR:InfoNoRecords; MX:1; A:1; LANG:en; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-originalarrivaltime: 01 Aug 2017 10:20:35.0892 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: HE1PR08MB2666 ping From: Wilco Dijkstra Sent: 20 July 2017 13:49 To: GCC Patches; James Greenhalgh Cc: nd Subject: [PATCH][AArch64] Improve addressing of TI/TFmode   In https://gcc.gnu.org/ml/gcc-patches/2017-06/msg01125.html Jiong pointed out some addressing inefficiencies due to a recent change in regcprop (https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00775.html). This patch improves aarch64_legitimize_address_displacement to split unaligned offsets of TImode and TFmode accesses.  The resulting code is better and no longer relies on the original regcprop optimization. For the test we now produce:         add     x1, sp, 4         stp     xzr, xzr, [x1, 24] rather than:         mov     x1, sp         add     x1, x1, 28         stp     xzr, xzr, [x1] OK for commit? ChangeLog: 2017-06-20  Wilco Dijkstra          * config/aarch64/aarch64.c (aarch64_legitimize_address_displacement):         Improve unaligned TImode/TFmode base/offset split. testsuite         * gcc.target/aarch64/ldp_stp_unaligned_2.c: New file. diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 90f248025a4fa928ebac657b689010f74dd100b5..208fdbe7262a93ee8caada2868a8d447de619c6e 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -4705,15 +4705,17 @@ aarch64_legitimate_address_p (machine_mode mode, rtx x,  /* Split an out-of-range address displacement into a base and offset.     Use 4KB range for 1- and 2-byte accesses and a 16KB range otherwise     to increase opportunities for sharing the base address of different sizes. -   For unaligned accesses and TI/TF mode use the signed 9-bit range.  */ +   Unaligned accesses use the signed 9-bit range, TImode/TFmode use +   the intersection of signed scaled 7-bit and signed 9-bit offset.  */  static bool  aarch64_legitimize_address_displacement (rtx *disp, rtx *off, machine_mode mode)  {    HOST_WIDE_INT offset = INTVAL (*disp);    HOST_WIDE_INT base = offset & ~(GET_MODE_SIZE (mode) < 4 ? 0xfff : 0x3ffc);   -  if (mode == TImode || mode == TFmode -      || (offset & (GET_MODE_SIZE (mode) - 1)) != 0) +  if (mode == TImode || mode == TFmode) +    base = (offset + 0x100) & ~0x1f8; +  else if ((offset & (GET_MODE_SIZE (mode) - 1)) != 0)      base = (offset + 0x100) & ~0x1ff;      *off = GEN_INT (base); diff --git a/gcc/testsuite/gcc.target/aarch64/ldp_stp_unaligned_2.c b/gcc/testsuite/gcc.target/aarch64/ldp_stp_unaligned_2.c new file mode 100644 index 0000000000000000000000000000000000000000..1e46755a39a0b97fa7af704086f82ffd5a216fb4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/ldp_stp_unaligned_2.c @@ -0,0 +1,18 @@ +/* { dg-options "-O2 -fomit-frame-pointer" } */ + +/* Check that we split unaligned LDP/STP into base and aligned offset.  */ + +typedef struct +{ +  int a, b, c, d, e; +} S; + +void foo (S *); + +void test (int x) +{ +  S s = { .a = x }; +  foo (&s); +} + +/* { dg-final { scan-assembler-not "mov\tx\[0-9\]+, sp" } } */