From patchwork Wed Nov 12 17:05:02 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Moore, Catherine" X-Patchwork-Id: 410044 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 8C6CC1400AB for ; Thu, 13 Nov 2014 04:05:20 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:references:in-reply-to :content-type:content-transfer-encoding:mime-version; q=dns; s= default; b=qftxAxVuQeVv/3StIgoQE2SRBvGiUESZ7vVNGBHzRY4F6nYd0GNet LMHwSMm8kKyUmgrUf9yvBgLh+pyUOosKoTplI6+z9BXa6M6vRrw/2PJgX62Tm2ec M6QowJzrfvW7ZScqNFXTPjxNX4XdFTHzA5ZZQvVBq3erI3vf5zXYlk= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:references:in-reply-to :content-type:content-transfer-encoding:mime-version; s=default; bh=QkdZgg4gs3hjrQbvex/eI/Geu3I=; b=IMdOp6/AcCTmGyY50E5splOs850W gg8/VAZ0s5uC0khdF0BAWeFCqcLGeKtDqpDZaoyrmIXX0O0ucGfd5FoGlEquVKxF 3L/21VgiNDbnRBGY960SQketP0APCAXzpIPm64JPELa5tHYFa2H201m/RYPBRsw9 qXJ/3XpArQP+yqM= Received: (qmail 16068 invoked by alias); 12 Nov 2014 17:05:12 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 16058 invoked by uid 89); 12 Nov 2014 17:05:12 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.1 required=5.0 tests=AWL, BAYES_05, RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.2 X-HELO: relay1.mentorg.com Received: from relay1.mentorg.com (HELO relay1.mentorg.com) (192.94.38.131) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 12 Nov 2014 17:05:10 +0000 Received: from svr-orw-fem-02x.mgc.mentorg.com ([147.34.96.206] helo=SVR-ORW-FEM-02.mgc.mentorg.com) by relay1.mentorg.com with esmtp id 1XobLu-0006Uw-GT from Catherine_Moore@mentor.com ; Wed, 12 Nov 2014 09:05:06 -0800 Received: from NA-MBX-01.mgc.mentorg.com ([169.254.1.141]) by SVR-ORW-FEM-02.mgc.mentorg.com ([147.34.96.168]) with mapi id 14.03.0181.006; Wed, 12 Nov 2014 09:05:03 -0800 From: "Moore, Catherine" To: Matthew Fortune , "'gcc-patches@gcc.gnu.org' (gcc-patches@gcc.gnu.org)" , "Eric Christopher (echristo@gmail.com)" CC: Richard Sandiford , Rich Fuhler , "Rozycki, Maciej" , "Myers, Joseph" Subject: RE: [PATCHv4][MIPS] Implement O32 ABI extensions (GCC) Date: Wed, 12 Nov 2014 17:05:02 +0000 Message-ID: References: <6D39441BF12EF246A7ABCE6654B0235320F6BF71@LEMAIL01.le.imgtec.org> In-Reply-To: <6D39441BF12EF246A7ABCE6654B0235320F6BF71@LEMAIL01.le.imgtec.org> MIME-Version: 1.0 Hi Matthew, > -----Original Message----- > From: Matthew Fortune [mailto:Matthew.Fortune@imgtec.com] > Sent: Thursday, November 06, 2014 12:11 PM > To: Moore, Catherine; 'gcc-patches@gcc.gnu.org' (gcc- > patches@gcc.gnu.org); Eric Christopher (echristo@gmail.com) > Cc: Richard Sandiford; Rich Fuhler; Rozycki, Maciej; Myers, Joseph > Subject: RE: [PATCHv4][MIPS] Implement O32 ABI extensions (GCC) > > Sorry to follow myself up. I realised that the new configure options should be > documented in install.texi. The only change from V3 is the doc/install.texi > change. > > The MIPS64 tests have completed without regression. > > Regards, > Matthew > > gcc/ > * common/config/mips/mips-common.c (mips_handle_option): > Ensure > that -mfp32, -mfp64 disable -mfpxx and -mfpxx disables -mfp64. > * config.gcc (--with-fp-32): New option. > (--with-odd-spreg-32): Likewise. > * config.in (HAVE_AS_DOT_MODULE): New config define. > * config/mips/mips-protos.h > (mips_secondary_memory_needed): New prototype. > (mips_hard_regno_caller_save_mode): Likewise. > * config/mips/mips.c (mips_get_reg_raw_mode): New static > prototype. > (mips_get_arg_info): Assert that V2SFmode is only handled specially > with TARGET_PAIRED_SINGLE_FLOAT. > (mips_return_mode_in_fpr_p): Likewise. > (mips16_call_stub_mode_suffix): Likewise. > (mips_get_reg_raw_mode): New static function. > (mips_return_fpr_pair): O32 return values span two registers. > (mips16_build_call_stub): Likewise. > (mips_function_value_regno_p): Support both FP return registers. > (mips_output_64bit_xfer): Use mthc1 whenever > TARGET_HAS_MXHC1. Add > specific cases for TARGET_FPXX to move via memory. > (mips_dwarf_register_span): For TARGET_FPXX pretend that modes > larger > than UNITS_PER_FPREG 'span' one register. > (mips_dwarf_frame_reg_mode): New static function. > (mips_file_start): Switch to using .module instead of .gnu_attribute. > No longer support FP ABI 4 (-mips32r2 -mfp64), replace with FP ABI 6. > Add FP ABI 5 (-mfpxx) and FP ABI 7 (-mfp64 -mno-odd-spreg). > (mips_save_reg, mips_restore_reg): Always represent DFmode > frame > slots with two CFI directives even for O32 FP64. > (mips_for_each_saved_gpr_and_fpr): Account for fixed_regs when > saving/restoring callee-saved registers. > (mips_hard_regno_mode_ok_p): Implement O32 FP64A extension. > (mips_secondary_memory_needed): New function. > (mips_option_override): ABI check for TARGET_FLOATXX. Disable > odd-numbered single-precision registers when using > TARGET_FLOATXX. > Implement -modd-spreg and defaults. > (mips_conditional_register_usage): Redefine O32 FP64 to match O32 > FP32 > callee-saved behaviour. > (mips_hard_regno_caller_save_mode): Implement. > (TARGET_GET_RAW_RESULT_MODE): Define target hook. > (TARGET_GET_RAW_ARG_MODE): Define target hook. > (TARGET_DWARF_FRAME_REG_MODE): Define target hook. > * config/mips/mips.h (TARGET_FLOAT32): New macro. > (TARGET_O32_FP64A_ABI): Likewise. > (TARGET_CPU_CPP_BUILTINS): TARGET_FPXX is __mips_fpr==0. > Add > _MIPS_SPFPSET builtin define. > (MIPS_FPXX_OPTION_SPEC): New macro. > (OPTION_DEFAULT_SPECS): Pass through --with-fp-32=* to -mfp and > --with-odd-spreg-32=* to -m[no-]odd-spreg. > (ISA_HAS_ODD_SPREG): New macro. > (ISA_HAS_MXHC1): True for anything other than -mfp32. > (ASM_SPEC): Pass through mfpxx, mfp64, -mno-odd-spreg and - > modd-spreg. > (MIN_FPRS_PER_FMT): Redefine in terms of TARGET_ODD_SPREG. > (HARD_REGNO_CALLER_SAVE_MODE): Define. Implement O32 > FPXX extension > (HARD_REGNO_CALL_PART_CLOBBERED): Likewise. > (SECONDARY_MEMORY_NEEDED): Likewise. > (FUNCTION_ARG_REGNO_P): Update for O32 FPXX and FP64 > extensions. > * config/mips/mips.md (define_attr enabled): Implement O32 FPXX > and > FP64A ABI extensions. > (move_doubleword_fpr): Use ISA_HAS_MXHC1 instead of > TARGET_FLOAT64. > * config/mips/mips.opt (mfpxx): New target option. > (modd-spreg): Likewise. > * config/mips/mti-elf.h (DRIVER_SELF_SPECS): Infer FP ABI from > arch. > * config/mips/mti-linux.h (DRIVER_SELF_SPECS): Likewise and > remove > fp64 sysroot. > * config/mips/t-mti-elf: Remove fp64 multilib. > * config/mips/t-mti-linux: Likewise. > * configure.ac: Detect .module support. > * configure: Regenerate. > * doc/invoke.texi: Document -mfpxx, -modd-spreg, -mno-odd-spreg > option. > * doc/install.texi (--with-fp-32, --with-odd-spreg-32): Document new > options. > > gcc/testsuite/ > * gcc.target/mips/args-1.c: Handle __mips_fpr == 0. > * gcc.target/mips/call-clobbered-1.c: New. > * gcc.target/mips/call-clobbered-2.c: New. > * gcc.target/mips/call-clobbered-3.c: New. > * gcc.target/mips/call-clobbered-4.c: New. > * gcc.target/mips/call-clobbered-5.c: New. > * gcc.target/mips/call-saved-4.c: New. > * gcc.target/mips/call-saved-5.c: New. > * gcc.target/mips/call-saved-6.c: New. > * gcc.target/mips/mips.exp: Support -mfpxx, -ffixed-f*, > and -m[no-]odd-spreg. Use _MIPS_SPFPSET to determine default > odd-spreg option. Account for -modd-spreg in minimum arch code. > * gcc.target/mips/movdf-1.c: New. > * gcc.target/mips/movdf-2.c: New. > * gcc.target/mips/movdf-3.c: New. > * gcc.target/mips/oddspreg-1.c: New. > * gcc.target/mips/oddspreg-2.c: New. > * gcc.target/mips/oddspreg-3.c: New. > * gcc.target/mips/oddspreg-4.c: New. > * gcc.target/mips/oddspreg-5.c: New. > * gcc.target/mips/oddspreg-6.c: New. > > libgcc/ > * config/mips/mips16.S: Set .module when supported. Update O32 > FP64 calling convention and use for FPXX when possible. Add FPXX > calling convention fallback case. The patch looks good. Please fix up these couple of nits prior to committing. Catherine /* Implement TARGET_CASE_VALUES_THRESHOLD. */ unsigned int cmoore@build6-lucid-cs:~$ Index: gcc/doc/invoke.texi =================================================================== --- gcc/doc/invoke.texi (revision 217363) +++ gcc/doc/invoke.texi (working copy) @@ -17865,6 +17883,15 @@ operations. Assume that the floating-point coprocessor supports double-precision operations. This is the default. +@item -modd-spreg +@itemx -mno-odd-spreg +@opindex modd-spreg +@opindex mno-odd-spreg +Enable the use of odd-numbered single-precision floating-point registers +for the o32 ABI. This is the default for processors that are known to +known to support these registers. When using the o32 FPXX ABI, +@code{-mno-odd-spreg} is set by default. + extra "known to" here. @item -mabs=2008 @itemx -mabs=legacy @opindex mabs=2008 Index: gcc/doc/install.texi =================================================================== --- gcc/doc/install.texi (revision 217363) +++ gcc/doc/install.texi (working copy) @@ -1256,6 +1256,33 @@ ISA for floating-point arithmetics. You can selec enables @option{-msse2} or @samp{avx} which enables @option{-mavx} by default. This option is only supported on i386 and x86-64 targets. +@item --with-fp-32=@var{mode} +On MIPS targets, set the default value for the @option{-mfp} option when using +the o32 ABI. The possibilities for @var{mode} are: +@table @code +@item 32 +Use the o32 FP32 ABI extension, as with the @option{-mfp32} command-line +option. +@item xx +Use the o32 FPXX ABI extension, as with the @option{-mfpxx} command-line +option. +@item 64 +Use the o32 FP64 ABI extension, as with the @option{-mfp64} command-line +option. +@end table +In the absence of this configuration option the default convention is to use +the o32 FP32 ABI extension. + s/default convention/default/ +@item --with-odd-spreg-32 +On MIPS targets, set the @option{-modd-spreg} option by default when using +the o32 ABI. + +@item --without-odd-spreg-32 +On MIPS targets, set the @option{-mno-odd-spreg} option by default when using +the o32 ABI. This is normally used in conjunction with +@option{--with-fp-32=64} in order to target the o32 FP64A ABI extension by +default. + s/extension by default./extension./ @item --with-nan=@var{encoding} On MIPS targets, set the default encoding convention to use for the special not-a-number (NaN) IEEE 754 floating-point data. The Index: gcc/config/mips/mips.c =================================================================== --- gcc/config/mips/mips.c (revision 217363) +++ gcc/config/mips/mips.c (working copy) @@ -18824,6 +19000,21 @@ mips_expand_vec_minmax (rtx target, rtx op0, rtx o emit_insn (gen_rtx_SET (VOIDmode, target, x)); } +/* Implement HARD_REGNO_CALLER_SAVE_MODE. */ + +machine_mode +mips_hard_regno_caller_save_mode (unsigned int regno, + unsigned int nregs, + machine_mode mode) +{ + /* For performance, to avoid saving/restoring upper parts of a register, + we return MODE as save mode when MODE is not VOIDmode. */ s/performance, to/performance, / + if (mode == VOIDmode) + return choose_hard_reg_mode (regno, nregs, false); + else + return mode; +}