| Message ID | FD3DCEAC5B03E9408544A1E416F11242018910FCCD@NA-MBX-01.mgc.mentorg.com |
|---|---|
| State | New |
| Headers | show |
Moore, Catherine <Catherine_Moore@mentor.com> writes: > The patch looks good. Please fix up these couple of nits prior to > committing. OK, thanks for the second read through. One further amendment below, I'll aim to commit later today. > Index: gcc/config/mips/mips.c > =================================================================== > --- gcc/config/mips/mips.c (revision 217363) > +++ gcc/config/mips/mips.c (working copy) > @@ -18824,6 +19000,21 @@ mips_expand_vec_minmax (rtx target, rtx op0, rtx > o > emit_insn (gen_rtx_SET (VOIDmode, target, x)); } > > +/* Implement HARD_REGNO_CALLER_SAVE_MODE. */ > + > +machine_mode > +mips_hard_regno_caller_save_mode (unsigned int regno, > + unsigned int nregs, > + machine_mode mode) { > + /* For performance, to avoid saving/restoring upper parts of a > register, > + we return MODE as save mode when MODE is not VOIDmode. */ > > s/performance, to/performance, / > The second part of this sentence will need to change too I think: For performance, avoid saving/restoring upper parts of a register by returning MODE as save mode when the mode is known. Thanks, Matthew
> -----Original Message----- > From: Matthew Fortune [mailto:Matthew.Fortune@imgtec.com] > Sent: Wednesday, November 12, 2014 1:59 PM > To: Moore, Catherine; 'gcc-patches@gcc.gnu.org' (gcc- > patches@gcc.gnu.org); Eric Christopher (echristo@gmail.com) > Cc: Richard Sandiford; Rich Fuhler; Rozycki, Maciej; Myers, Joseph > Subject: RE: [PATCHv4][MIPS] Implement O32 ABI extensions (GCC) > > Moore, Catherine <Catherine_Moore@mentor.com> writes: > > The patch looks good. Please fix up these couple of nits prior to > > committing. > > OK, thanks for the second read through. One further amendment below, I'll > aim to commit later today. > Yes, that's better. > > Index: gcc/config/mips/mips.c > > > ========================================================== > ========= > > --- gcc/config/mips/mips.c (revision 217363) > > +++ gcc/config/mips/mips.c (working copy) > > @@ -18824,6 +19000,21 @@ mips_expand_vec_minmax (rtx target, rtx > op0, > > rtx o > > emit_insn (gen_rtx_SET (VOIDmode, target, x)); } > > > > +/* Implement HARD_REGNO_CALLER_SAVE_MODE. */ > > + > > +machine_mode > > +mips_hard_regno_caller_save_mode (unsigned int regno, > > + unsigned int nregs, > > + machine_mode mode) { > > + /* For performance, to avoid saving/restoring upper parts of a > > register, > > + we return MODE as save mode when MODE is not VOIDmode. */ > > > > s/performance, to/performance, / > > > > The second part of this sentence will need to change too I think: > > For performance, avoid saving/restoring upper parts of a register by > returning MODE as save mode when the mode is known. > > Thanks, > Matthew
> > Moore, Catherine <Catherine_Moore@mentor.com> writes: > > > The patch looks good. Please fix up these couple of nits prior to > > > committing. > > > > OK, thanks for the second read through. One further amendment below, > > I'll aim to commit later today. > > > > Yes, that's better. Committed as r217446 Fingers crossed there will be no fallout from it but if there is I'll deal with it promptly. Matthew
On Wed, Nov 12, 2014 at 2:56 PM, Matthew Fortune <Matthew.Fortune@imgtec.com> wrote: >> > Moore, Catherine <Catherine_Moore@mentor.com> writes: >> > > The patch looks good. Please fix up these couple of nits prior to >> > > committing. >> > >> > OK, thanks for the second read through. One further amendment below, >> > I'll aim to commit later today. >> > >> >> Yes, that's better. > > Committed as r217446 > > Fingers crossed there will be no fallout from it but if there is I'll deal > with it promptly. Most of the testcases fail if you are compiling for soft-float: FAIL: gcc.target/mips/call-clobbered-1.c -O1 scan-assembler-times sdc1 2 FAIL: gcc.target/mips/call-clobbered-1.c -O1 scan-assembler-times ldc1 4 ... FAIL: gcc.target/mips/call-clobbered-2.c -O1 scan-assembler-times lwc1 4 FAIL: gcc.target/mips/call-clobbered-2.c -O1 scan-assembler-times swc1 2 ... FAIL: gcc.target/mips/call-clobbered-3.c -O1 scan-assembler-times lwc1 5 FAIL: gcc.target/mips/call-clobbered-3.c -O1 scan-assembler-times swc1 3 ... FAIL: gcc.target/mips/call-clobbered-4.c -Os scan-assembler-times lwc1 4 FAIL: gcc.target/mips/call-clobbered-4.c -Os scan-assembler-times swc1 2 ... FAIL: gcc.target/mips/call-saved-4.c -O0 scan-assembler \\\\\$f20 FAIL: gcc.target/mips/call-saved-4.c -O0 scan-assembler \\\\\$f22 FAIL: gcc.target/mips/call-saved-4.c -O0 scan-assembler \\\\\$f24 FAIL: gcc.target/mips/call-saved-4.c -O0 scan-assembler \\\\\$f26 FAIL: gcc.target/mips/call-saved-4.c -O0 scan-assembler \\\\\$f28 FAIL: gcc.target/mips/call-saved-4.c -O0 scan-assembler \\\\\$f30 .... FAIL: gcc.target/mips/call-saved-5.c -O0 scan-assembler \\\\\$f20 FAIL: gcc.target/mips/call-saved-5.c -O0 scan-assembler \\\\\$f22 FAIL: gcc.target/mips/call-saved-5.c -O0 scan-assembler \\\\\$f24 FAIL: gcc.target/mips/call-saved-5.c -O0 scan-assembler \\\\\$f26 FAIL: gcc.target/mips/call-saved-5.c -O0 scan-assembler \\\\\$f28 FAIL: gcc.target/mips/call-saved-5.c -O0 scan-assembler \\\\\$f30 ... FAIL: gcc.target/mips/movdf-1.c -O1 scan-assembler-times ldc1 1 ... FAIL: gcc.target/mips/movdf-2.c -O1 scan-assembler mthc1 FAIL: gcc.target/mips/movdf-2.c -O1 scan-assembler mtc1 ... FAIL: gcc.target/mips/movdf-3.c -O1 scan-assembler-times mtc1 2 ... Thanks, Andrew Pinski > > Matthew
Andrew Pinski <pinskia@gmail.com> writes: > On Wed, Nov 12, 2014 at 2:56 PM, Matthew Fortune > <Matthew.Fortune@imgtec.com> wrote: > >> > Moore, Catherine <Catherine_Moore@mentor.com> writes: > >> > > The patch looks good. Please fix up these couple of nits prior to > >> > > committing. > >> > > >> > OK, thanks for the second read through. One further amendment > >> > below, I'll aim to commit later today. > >> > > >> > >> Yes, that's better. > > > > Committed as r217446 > > > > Fingers crossed there will be no fallout from it but if there is I'll > > deal with it promptly. > > Most of the testcases fail if you are compiling for soft-float: > FAIL: gcc.target/mips/call-clobbered-1.c -O1 scan-assembler-times sdc1 2 > FAIL: gcc.target/mips/call-clobbered-1.c -O1 scan-assembler-times ldc1 4 > ... > FAIL: gcc.target/mips/call-clobbered-2.c -O1 scan-assembler-times lwc1 4 > FAIL: gcc.target/mips/call-clobbered-2.c -O1 scan-assembler-times swc1 2 > ... > > FAIL: gcc.target/mips/call-clobbered-3.c -O1 scan-assembler-times lwc1 5 > FAIL: gcc.target/mips/call-clobbered-3.c -O1 scan-assembler-times swc1 3 > ... > FAIL: gcc.target/mips/call-clobbered-4.c -Os scan-assembler-times lwc1 4 > FAIL: gcc.target/mips/call-clobbered-4.c -Os scan-assembler-times swc1 2 > ... > FAIL: gcc.target/mips/call-saved-4.c -O0 scan-assembler \\\\\$f20 > FAIL: gcc.target/mips/call-saved-4.c -O0 scan-assembler \\\\\$f22 > FAIL: gcc.target/mips/call-saved-4.c -O0 scan-assembler \\\\\$f24 > FAIL: gcc.target/mips/call-saved-4.c -O0 scan-assembler \\\\\$f26 > FAIL: gcc.target/mips/call-saved-4.c -O0 scan-assembler \\\\\$f28 > FAIL: gcc.target/mips/call-saved-4.c -O0 scan-assembler \\\\\$f30 > .... > > FAIL: gcc.target/mips/call-saved-5.c -O0 scan-assembler \\\\\$f20 > FAIL: gcc.target/mips/call-saved-5.c -O0 scan-assembler \\\\\$f22 > FAIL: gcc.target/mips/call-saved-5.c -O0 scan-assembler \\\\\$f24 > FAIL: gcc.target/mips/call-saved-5.c -O0 scan-assembler \\\\\$f26 > FAIL: gcc.target/mips/call-saved-5.c -O0 scan-assembler \\\\\$f28 > FAIL: gcc.target/mips/call-saved-5.c -O0 scan-assembler \\\\\$f30 > ... > FAIL: gcc.target/mips/movdf-1.c -O1 scan-assembler-times ldc1 1 > ... > FAIL: gcc.target/mips/movdf-2.c -O1 scan-assembler mthc1 > FAIL: gcc.target/mips/movdf-2.c -O1 scan-assembler mtc1 > ... > FAIL: gcc.target/mips/movdf-3.c -O1 scan-assembler-times mtc1 2 > ... Thanks Andrew. I'll take a look, getting these tests to be usable in all the hardfloat configs took such a long time that I have clearly not run the single or soft float configs. My intention was to make mips.exp intelligent enough to know that -mfp* imply -mdouble-float and -mhard-float which should resolve this. I would also add -msingle-float support but single-float has been ignored for a number of tests so I'll look at that separately. It will take a couple of days to go through the configs to make sure I don’t break the tests for hard-float configs with the change. Matthew
Index: gcc/doc/invoke.texi =================================================================== --- gcc/doc/invoke.texi (revision 217363) +++ gcc/doc/invoke.texi (working copy) @@ -17865,6 +17883,15 @@ operations. Assume that the floating-point coprocessor supports double-precision operations. This is the default. +@item -modd-spreg +@itemx -mno-odd-spreg +@opindex modd-spreg +@opindex mno-odd-spreg +Enable the use of odd-numbered single-precision floating-point registers +for the o32 ABI. This is the default for processors that are known to +known to support these registers. When using the o32 FPXX ABI, +@code{-mno-odd-spreg} is set by default. + extra "known to" here. @item -mabs=2008 @itemx -mabs=legacy @opindex mabs=2008 Index: gcc/doc/install.texi =================================================================== --- gcc/doc/install.texi (revision 217363) +++ gcc/doc/install.texi (working copy) @@ -1256,6 +1256,33 @@ ISA for floating-point arithmetics. You can selec enables @option{-msse2} or @samp{avx} which enables @option{-mavx} by default. This option is only supported on i386 and x86-64 targets. +@item --with-fp-32=@var{mode} +On MIPS targets, set the default value for the @option{-mfp} option when using +the o32 ABI. The possibilities for @var{mode} are: +@table @code +@item 32 +Use the o32 FP32 ABI extension, as with the @option{-mfp32} command-line +option. +@item xx +Use the o32 FPXX ABI extension, as with the @option{-mfpxx} command-line +option. +@item 64 +Use the o32 FP64 ABI extension, as with the @option{-mfp64} command-line +option. +@end table +In the absence of this configuration option the default convention is to use +the o32 FP32 ABI extension. + s/default convention/default/ +@item --with-odd-spreg-32 +On MIPS targets, set the @option{-modd-spreg} option by default when using +the o32 ABI. + +@item --without-odd-spreg-32 +On MIPS targets, set the @option{-mno-odd-spreg} option by default when using +the o32 ABI. This is normally used in conjunction with +@option{--with-fp-32=64} in order to target the o32 FP64A ABI extension by +default. + s/extension by default./extension./ @item --with-nan=@var{encoding} On MIPS targets, set the default encoding convention to use for the special not-a-number (NaN) IEEE 754 floating-point data. The Index: gcc/config/mips/mips.c =================================================================== --- gcc/config/mips/mips.c (revision 217363) +++ gcc/config/mips/mips.c (working copy) @@ -18824,6 +19000,21 @@ mips_expand_vec_minmax (rtx target, rtx op0, rtx o emit_insn (gen_rtx_SET (VOIDmode, target, x)); } +/* Implement HARD_REGNO_CALLER_SAVE_MODE. */ + +machine_mode +mips_hard_regno_caller_save_mode (unsigned int regno, + unsigned int nregs, + machine_mode mode) +{ + /* For performance, to avoid saving/restoring upper parts of a register, + we return MODE as save mode when MODE is not VOIDmode. */ s/performance, to/performance, / + if (mode == VOIDmode) + return choose_hard_reg_mode (regno, nregs, false); + else + return mode; +}