From patchwork Fri Jan 14 18:27:30 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Stump X-Patchwork-Id: 78987 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 1F41FB70B3 for ; Sat, 15 Jan 2011 05:27:43 +1100 (EST) Received: (qmail 7175 invoked by alias); 14 Jan 2011 18:27:42 -0000 Received: (qmail 7164 invoked by uid 22791); 14 Jan 2011 18:27:39 -0000 X-SWARE-Spam-Status: No, hits=-1.8 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, RFC_ABUSE_POST, T_RP_MATCHES_RCVD, T_TO_NO_BRKTS_FREEMAIL X-Spam-Check-By: sourceware.org Received: from qmta01.emeryville.ca.mail.comcast.net (HELO qmta01.emeryville.ca.mail.comcast.net) (76.96.30.16) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Fri, 14 Jan 2011 18:27:32 +0000 Received: from omta05.emeryville.ca.mail.comcast.net ([76.96.30.43]) by qmta01.emeryville.ca.mail.comcast.net with comcast id vScg1f0030vp7WLA1WTXp0; Fri, 14 Jan 2011 18:27:31 +0000 Received: from up.mrs.kithrup.com ([24.4.193.8]) by omta05.emeryville.ca.mail.comcast.net with comcast id vWTW1f0080BKwT48RWTWDQ; Fri, 14 Jan 2011 18:27:31 +0000 Subject: Re: [PATCH 09/14] rx: Cleanup non-VOIDmode SETs. Mime-Version: 1.0 (Apple Message framework v1082) From: Mike Stump In-Reply-To: <1295021309-28608-10-git-send-email-rth@redhat.com> Date: Fri, 14 Jan 2011 10:27:30 -0800 Cc: gcc-patches@gcc.gnu.org, nickc@redhat.com, Richard Henderson Message-Id: References: <1295021309-28608-1-git-send-email-rth@redhat.com> <1295021309-28608-10-git-send-email-rth@redhat.com> To: rth@redhat.com X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org On Jan 14, 2011, at 8:08 AM, rth@redhat.com wrote: > SET should always have VOIDmode. If that is really true... the below patch fixes all the remaining instances of this. Ok? Index: config/alpha/alpha.md =================================================================== --- config/alpha/alpha.md (revision 168796) +++ config/alpha/alpha.md (working copy) @@ -6910,13 +6910,13 @@ ;; Load the CIW into r2 for calling __T3E_MISMATCH (define_expand "umk_mismatch_args" - [(set:DI (match_dup 1) (mem:DI (plus:DI (reg:DI 15) (const_int -16)))) - (set:DI (match_dup 2) (mem:DI (plus:DI (match_dup 1) (const_int -32)))) - (set:DI (reg:DI 1) (match_operand:DI 0 "const_int_operand" "")) - (set:DI (match_dup 3) (plus:DI (mult:DI (reg:DI 25) - (const_int 8)) - (match_dup 2))) - (set:DI (reg:DI 2) (mem:DI (match_dup 3)))] + [(set (match_dup 1) (mem:DI (plus:DI (reg:DI 15) (const_int -16)))) + (set (match_dup 2) (mem:DI (plus:DI (match_dup 1) (const_int -32)))) + (set (reg:DI 1) (match_operand:DI 0 "const_int_operand" "")) + (set (match_dup 3) (plus:DI (mult:DI (reg:DI 25) + (const_int 8)) + (match_dup 2))) + (set (reg:DI 2) (mem:DI (match_dup 3)))] "TARGET_ABI_UNICOSMK" { operands[1] = gen_reg_rtx (DImode); Index: config/fr30/fr30.md =================================================================== --- config/fr30/fr30.md (revision 168797) +++ config/fr30/fr30.md (working copy) @@ -140,16 +140,16 @@ ;; Push a register onto the stack (define_insn "movsi_push" - [(set:SI (mem:SI (pre_dec:SI (reg:SI 15))) - (match_operand:SI 0 "register_operand" "a"))] + [(set (mem:SI (pre_dec:SI (reg:SI 15))) + (match_operand:SI 0 "register_operand" "a"))] "" "st %0, @-r15" ) ;; Pop a register off the stack (define_insn "movsi_pop" - [(set:SI (match_operand:SI 0 "register_operand" "=a") - (mem:SI (post_inc:SI (reg:SI 15))))] + [(set (match_operand:SI 0 "register_operand" "=a") + (mem:SI (post_inc:SI (reg:SI 15))))] "" "ld @r15+, %0" ) @@ -292,8 +292,8 @@ "INTVAL (operands[1]) <= -1 && INTVAL (operands[1]) >= -128 && (GET_CODE (operands[0]) != SUBREG || SCALAR_INT_MODE_P (GET_MODE (XEXP (operands[0], 0))))" - [(set:SI (match_dup 0) (match_dup 1)) - (set:SI (match_dup 0) (sign_extend:SI (match_dup 2)))] + [(set (match_dup 0) (match_dup 1)) + (set (match_dup 0) (sign_extend:SI (match_dup 2)))] "{ operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff); operands[2] = gen_lowpart (QImode, operands[0]); @@ -307,8 +307,8 @@ [(set (match_operand:SI 0 "register_operand" "") (match_operand:SI 1 "const_int_operand" ""))] "(INTVAL (operands[1]) < 0) && ((INTVAL (operands[1]) & 0x00ffffff) == 0)" - [(set:SI (match_dup 0) (match_dup 2)) - (parallel [(set:SI (match_dup 0) (ashift:SI (match_dup 0) (const_int 24))) + [(set (match_dup 0) (match_dup 2)) + (parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 24))) (clobber (reg:CC 16))])] "{ HOST_WIDE_INT val = INTVAL (operands[1]); @@ -325,8 +325,8 @@ (match_operand:SI 1 "const_int_operand" ""))] "(INTVAL (operands[1]) > 0x00ffffff) && ((INTVAL (operands[1]) >> exact_log2 (INTVAL (operands[1]) & (- INTVAL (operands[1])))) < 0x100)" - [(set:SI (match_dup 0) (match_dup 2)) - (parallel [(set:SI (match_dup 0) (ashift:SI (match_dup 0) (match_dup 3))) + [(set (match_dup 0) (match_dup 2)) + (parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 3))) (clobber (reg:CC 16))])] "{ HOST_WIDE_INT val = INTVAL (operands[1]); @@ -417,108 +417,108 @@ ;; is during function prologues and epilogues. (define_peephole - [(set:SI (mem:SI (pre_dec:SI (reg:SI 15))) - (match_operand:SI 0 "high_register_operand" "h")) - (set:SI (mem:SI (pre_dec:SI (reg:SI 15))) - (match_operand:SI 1 "high_register_operand" "h")) - (set:SI (mem:SI (pre_dec:SI (reg:SI 15))) - (match_operand:SI 2 "high_register_operand" "h")) - (set:SI (mem:SI (pre_dec:SI (reg:SI 15))) - (match_operand:SI 3 "high_register_operand" "h"))] + [(set (mem:SI (pre_dec:SI (reg:SI 15))) + (match_operand:SI 0 "high_register_operand" "h")) + (set (mem:SI (pre_dec:SI (reg:SI 15))) + (match_operand:SI 1 "high_register_operand" "h")) + (set (mem:SI (pre_dec:SI (reg:SI 15))) + (match_operand:SI 2 "high_register_operand" "h")) + (set (mem:SI (pre_dec:SI (reg:SI 15))) + (match_operand:SI 3 "high_register_operand" "h"))] "fr30_check_multiple_regs (operands, 4, 1)" "stm1 (%0, %1, %2, %3)" [(set_attr "delay_type" "other")] ) (define_peephole - [(set:SI (mem:SI (pre_dec:SI (reg:SI 15))) - (match_operand:SI 0 "high_register_operand" "h")) - (set:SI (mem:SI (pre_dec:SI (reg:SI 15))) - (match_operand:SI 1 "high_register_operand" "h")) - (set:SI (mem:SI (pre_dec:SI (reg:SI 15))) - (match_operand:SI 2 "high_register_operand" "h"))] + [(set (mem:SI (pre_dec:SI (reg:SI 15))) + (match_operand:SI 0 "high_register_operand" "h")) + (set (mem:SI (pre_dec:SI (reg:SI 15))) + (match_operand:SI 1 "high_register_operand" "h")) + (set (mem:SI (pre_dec:SI (reg:SI 15))) + (match_operand:SI 2 "high_register_operand" "h"))] "fr30_check_multiple_regs (operands, 3, 1)" "stm1 (%0, %1, %2)" [(set_attr "delay_type" "other")] ) (define_peephole - [(set:SI (mem:SI (pre_dec:SI (reg:SI 15))) - (match_operand:SI 0 "high_register_operand" "h")) - (set:SI (mem:SI (pre_dec:SI (reg:SI 15))) - (match_operand:SI 1 "high_register_operand" "h"))] + [(set (mem:SI (pre_dec:SI (reg:SI 15))) + (match_operand:SI 0 "high_register_operand" "h")) + (set (mem:SI (pre_dec:SI (reg:SI 15))) + (match_operand:SI 1 "high_register_operand" "h"))] "fr30_check_multiple_regs (operands, 2, 1)" "stm1 (%0, %1)" [(set_attr "delay_type" "other")] ) (define_peephole - [(set:SI (match_operand:SI 0 "high_register_operand" "h") - (mem:SI (post_inc:SI (reg:SI 15)))) - (set:SI (match_operand:SI 1 "high_register_operand" "h") - (mem:SI (post_inc:SI (reg:SI 15)))) - (set:SI (match_operand:SI 2 "high_register_operand" "h") - (mem:SI (post_inc:SI (reg:SI 15)))) - (set:SI (match_operand:SI 3 "high_register_operand" "h") - (mem:SI (post_inc:SI (reg:SI 15))))] + [(set (match_operand:SI 0 "high_register_operand" "h") + (mem:SI (post_inc:SI (reg:SI 15)))) + (set (match_operand:SI 1 "high_register_operand" "h") + (mem:SI (post_inc:SI (reg:SI 15)))) + (set (match_operand:SI 2 "high_register_operand" "h") + (mem:SI (post_inc:SI (reg:SI 15)))) + (set (match_operand:SI 3 "high_register_operand" "h") + (mem:SI (post_inc:SI (reg:SI 15))))] "fr30_check_multiple_regs (operands, 4, 0)" "ldm1 (%0, %1, %2, %3)" [(set_attr "delay_type" "other")] ) (define_peephole - [(set:SI (match_operand:SI 0 "high_register_operand" "h") - (mem:SI (post_inc:SI (reg:SI 15)))) - (set:SI (match_operand:SI 1 "high_register_operand" "h") - (mem:SI (post_inc:SI (reg:SI 15)))) - (set:SI (match_operand:SI 2 "high_register_operand" "h") - (mem:SI (post_inc:SI (reg:SI 15))))] + [(set (match_operand:SI 0 "high_register_operand" "h") + (mem:SI (post_inc:SI (reg:SI 15)))) + (set (match_operand:SI 1 "high_register_operand" "h") + (mem:SI (post_inc:SI (reg:SI 15)))) + (set (match_operand:SI 2 "high_register_operand" "h") + (mem:SI (post_inc:SI (reg:SI 15))))] "fr30_check_multiple_regs (operands, 3, 0)" "ldm1 (%0, %1, %2)" [(set_attr "delay_type" "other")] ) (define_peephole - [(set:SI (match_operand:SI 0 "high_register_operand" "h") - (mem:SI (post_inc:SI (reg:SI 15)))) - (set:SI (match_operand:SI 1 "high_register_operand" "h") - (mem:SI (post_inc:SI (reg:SI 15))))] + [(set (match_operand:SI 0 "high_register_operand" "h") + (mem:SI (post_inc:SI (reg:SI 15)))) + (set (match_operand:SI 1 "high_register_operand" "h") + (mem:SI (post_inc:SI (reg:SI 15))))] "fr30_check_multiple_regs (operands, 2, 0)" "ldm1 (%0, %1)" [(set_attr "delay_type" "other")] ) (define_peephole - [(set:SI (mem:SI (pre_dec:SI (reg:SI 15))) - (match_operand:SI 0 "low_register_operand" "l")) - (set:SI (mem:SI (pre_dec:SI (reg:SI 15))) - (match_operand:SI 1 "low_register_operand" "l")) - (set:SI (mem:SI (pre_dec:SI (reg:SI 15))) - (match_operand:SI 2 "low_register_operand" "l")) - (set:SI (mem:SI (pre_dec:SI (reg:SI 15))) - (match_operand:SI 3 "low_register_operand" "l"))] + [(set (mem:SI (pre_dec:SI (reg:SI 15))) + (match_operand:SI 0 "low_register_operand" "l")) + (set (mem:SI (pre_dec:SI (reg:SI 15))) + (match_operand:SI 1 "low_register_operand" "l")) + (set (mem:SI (pre_dec:SI (reg:SI 15))) + (match_operand:SI 2 "low_register_operand" "l")) + (set (mem:SI (pre_dec:SI (reg:SI 15))) + (match_operand:SI 3 "low_register_operand" "l"))] "fr30_check_multiple_regs (operands, 4, 1)" "stm0 (%0, %1, %2, %3)" [(set_attr "delay_type" "other")] ) (define_peephole - [(set:SI (mem:SI (pre_dec:SI (reg:SI 15))) - (match_operand:SI 0 "low_register_operand" "l")) - (set:SI (mem:SI (pre_dec:SI (reg:SI 15))) - (match_operand:SI 1 "low_register_operand" "l")) - (set:SI (mem:SI (pre_dec:SI (reg:SI 15))) - (match_operand:SI 2 "low_register_operand" "l"))] + [(set (mem:SI (pre_dec:SI (reg:SI 15))) + (match_operand:SI 0 "low_register_operand" "l")) + (set (mem:SI (pre_dec:SI (reg:SI 15))) + (match_operand:SI 1 "low_register_operand" "l")) + (set (mem:SI (pre_dec:SI (reg:SI 15))) + (match_operand:SI 2 "low_register_operand" "l"))] "fr30_check_multiple_regs (operands, 3, 1)" "stm0 (%0, %1, %2)" [(set_attr "delay_type" "other")] ) (define_peephole - [(set:SI (mem:SI (pre_dec:SI (reg:SI 15))) - (match_operand:SI 0 "low_register_operand" "l")) - (set:SI (mem:SI (pre_dec:SI (reg:SI 15))) - (match_operand:SI 1 "low_register_operand" "l"))] + [(set (mem:SI (pre_dec:SI (reg:SI 15))) + (match_operand:SI 0 "low_register_operand" "l")) + (set (mem:SI (pre_dec:SI (reg:SI 15))) + (match_operand:SI 1 "low_register_operand" "l"))] "fr30_check_multiple_regs (operands, 2, 1)" "stm0 (%0, %1)" [(set_attr "delay_type" "other")] @@ -1210,15 +1210,15 @@ (define_expand "enter_func" [(parallel - [(set:SI (mem:SI (minus:SI (match_dup 1) - (const_int 4))) - (match_dup 2)) - (set:SI (match_dup 2) - (minus:SI (match_dup 1) - (const_int 4))) - (set:SI (match_dup 1) - (minus:SI (match_dup 1) - (match_operand:SI 0 "immediate_operand")))] + [(set (mem:SI (minus:SI (match_dup 1) + (const_int 4))) + (match_dup 2)) + (set (match_dup 2) + (minus:SI (match_dup 1) + (const_int 4))) + (set (match_dup 1) + (minus:SI (match_dup 1) + (match_operand:SI 0 "immediate_operand")))] )] "" { @@ -1227,15 +1227,15 @@ }) (define_insn "*enter_func" - [(set:SI (mem:SI (minus:SI (reg:SI 15) - (const_int 4))) - (reg:SI 14)) - (set:SI (reg:SI 14) - (minus:SI (reg:SI 15) - (const_int 4))) - (set:SI (reg:SI 15) - (minus:SI (reg:SI 15) - (match_operand 0 "immediate_operand" "i")))] + [(set (mem:SI (minus:SI (reg:SI 15) + (const_int 4))) + (reg:SI 14)) + (set (reg:SI 14) + (minus:SI (reg:SI 15) + (const_int 4))) + (set (reg:SI 15) + (minus:SI (reg:SI 15) + (match_operand 0 "immediate_operand" "i")))] "reload_completed" "enter #%0" [(set_attr "delay_type" "other")] Index: config/moxie/moxie.md =================================================================== --- config/moxie/moxie.md (revision 168796) +++ config/moxie/moxie.md (working copy) @@ -188,15 +188,15 @@ ;; Push a register onto the stack (define_insn "movsi_push" - [(set:SI (mem:SI (pre_dec:SI (reg:SI 1))) - (match_operand:SI 0 "register_operand" "r"))] + [(set (mem:SI (pre_dec:SI (reg:SI 1))) + (match_operand:SI 0 "register_operand" "r"))] "" "push $sp, %0") ;; Pop a register from the stack (define_insn "movsi_pop" - [(set:SI (match_operand:SI 1 "register_operand" "=r") - (mem:SI (post_inc:SI (match_operand:SI 0 "register_operand" "r"))))] + [(set (match_operand:SI 1 "register_operand" "=r") + (mem:SI (post_inc:SI (match_operand:SI 0 "register_operand" "r"))))] "" "pop %0, %1") Index: config/arm/iwmmxt.md =================================================================== --- config/arm/iwmmxt.md (revision 168796) +++ config/arm/iwmmxt.md (working copy) @@ -551,7 +551,7 @@ ;; ;; Note - you cannot use patterns like these here: ;; -;; (set: (match:) (: (match:) (match:))) +;; (set (match:) (: (match:) (match:))) ;; ;; Because GCC will assume that the truth value (1 or 0) is installed ;; into the entire destination vector, (with the '1' going into the least