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Thu, 14 Nov 2019 19:13:13 +0000 From: Srinath Parvathaneni To: "gcc-patches@gcc.gnu.org" CC: Richard Earnshaw , Kyrylo Tkachov Subject: [PATCH][ARM][GCC][1/4x]: MVE intrinsics with quaternary operands. Date: Thu, 14 Nov 2019 19:13:13 +0000 Message-ID: References: <157375666998.31400.16652205595246718910.scripted-patch-series@arm.com> In-Reply-To: <157375666998.31400.16652205595246718910.scripted-patch-series@arm.com> Authentication-Results-Original: spf=none (sender IP is ) smtp.mailfrom=Srinath.Parvathaneni@arm.com; X-MS-Exchange-PUrlCount: 1 x-ms-exchange-transport-forked: True x-checkrecipientrouted: true x-ms-oob-tlc-oobclassifiers: OLM:529;OLM:529; X-Forefront-Antispam-Report-Untrusted: SFV:NSPM; SFS:(10009020)(1496009)(4636009)(39860400002)(396003)(366004)(376002)(346002)(136003)(54534003)(199004)(189003)(81156014)(316002)(81166006)(30864003)(2501003)(44832011)(4326008)(74316002)(7696005)(99286004)(478600001)(186003)(11346002)(26005)(54906003)(76176011)(52536014)(5660300002)(446003)(25786009)(71190400001)(71200400001)(33656002)(66946007)(52116002)(305945005)(66556008)(7736002)(66446008)(66476007)(66616009)(64756008)(256004)(5024004)(9686003)(966005)(5640700003)(3846002)(66066001)(4001150100001)(6916009)(86362001)(486006)(6506007)(6436002)(14454004)(8936002)(2906002)(6116002)(2351001)(55016002)(8676002)(102836004)(386003)(476003)(6306002)(579004)(559001)(569006); DIR:OUT; SFP:1101; SCL:1; SRVR:DBBPR08MB4807; H:DBBPR08MB4775.eurprd08.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: BxQcrytWr32lMgCdjbZZ4uXO/qFKYR8ljsU9/1jmWVHpnrvEEHK4zhw4v2sI50mqrGcpH4gQXwsWz09dd3prkdIKY6+jGK2c2BKKhw4VzeZRE11CIgHLi9kJKlHq3V5Nw9U1KpkOoorsyDtVQ7xOiE1J1DCuu2F9E5RB3hzyn5byVl1lk99pPTzwQc3Y+241PBt0dKiZ0Kdngq41oFY032I0rKTbMq6Q6o1/JabpiXLjS/Nr+vXehiIeG9iZoTdDh7k3Pgl4Tl40/g69VCYGea6oLdGwjW0HvF5wTUtixqZM1d1gBdurQzu7U2c4Qy/Siw7jwOpAEytyLq/0wnmEtBgKyn2Vrv7fJC8yN4T4oLm4P9RSu4U4VwFWOobbYIvmC98WBab52+akYImZBI20kQ1NfV15Jl9sJjs7p0n+syTy5urJ3labK9npB7MczxntQyQKbBlugumPzFNkW8QD91OGFECEB5T7ItAadiqjBQo= MIME-Version: 1.0 Original-Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Srinath.Parvathaneni@arm.com; X-MS-Exchange-Transport-CrossTenantHeadersStripped: VE1EUR03FT032.eop-EUR03.prod.protection.outlook.com X-MS-Office365-Filtering-Correlation-Id-Prvs: 67dad186-e319-461d-08ac-08d76936b22b X-IsSubscribed: yes Hello, This patch supports following MVE ACLE intrinsics with quaternary operands. vsriq_m_n_s8, vsubq_m_s8, vsubq_x_s8, vcvtq_m_n_f16_u16, vcvtq_x_n_f16_u16, vqshluq_m_n_s8, vabavq_p_s8, vsriq_m_n_u8, vshlq_m_u8, vshlq_x_u8, vsubq_m_u8, vsubq_x_u8, vabavq_p_u8, vshlq_m_s8, vshlq_x_s8, vcvtq_m_n_f16_s16, vcvtq_x_n_f16_s16, vsriq_m_n_s16, vsubq_m_s16, vsubq_x_s16, vcvtq_m_n_f32_u32, vcvtq_x_n_f32_u32, vqshluq_m_n_s16, vabavq_p_s16, vsriq_m_n_u16, vshlq_m_u16, vshlq_x_u16, vsubq_m_u16, vsubq_x_u16, vabavq_p_u16, vshlq_m_s16, vshlq_x_s16, vcvtq_m_n_f32_s32, vcvtq_x_n_f32_s32, vsriq_m_n_s32, vsubq_m_s32, vsubq_x_s32, vqshluq_m_n_s32, vabavq_p_s32, vsriq_m_n_u32, vshlq_m_u32, vshlq_x_u32, vsubq_m_u32, vsubq_x_u32, vabavq_p_u32, vshlq_m_s32, vshlq_x_s32. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics Regression tested on arm-none-eabi and found no regressions. Ok for trunk? Thanks, Srinath. gcc/ChangeLog: 2019-10-29 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm-builtins.c (QUADOP_UNONE_UNONE_NONE_NONE_UNONE_QUALIFIERS): Define builtin qualifier. (QUADOP_NONE_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise. (QUADOP_NONE_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise. (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise. (QUADOP_UNONE_UNONE_NONE_IMM_UNONE_QUALIFIERS): Likewise. (QUADOP_NONE_NONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise. (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise. (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise. * config/arm/arm_mve.h (vsriq_m_n_s8): Define macro. (vsubq_m_s8): Likewise. (vcvtq_m_n_f16_u16): Likewise. (vqshluq_m_n_s8): Likewise. (vabavq_p_s8): Likewise. (vsriq_m_n_u8): Likewise. (vshlq_m_u8): Likewise. (vsubq_m_u8): Likewise. (vabavq_p_u8): Likewise. (vshlq_m_s8): Likewise. (vcvtq_m_n_f16_s16): Likewise. (vsriq_m_n_s16): Likewise. (vsubq_m_s16): Likewise. (vcvtq_m_n_f32_u32): Likewise. (vqshluq_m_n_s16): Likewise. (vabavq_p_s16): Likewise. (vsriq_m_n_u16): Likewise. (vshlq_m_u16): Likewise. (vsubq_m_u16): Likewise. (vabavq_p_u16): Likewise. (vshlq_m_s16): Likewise. (vcvtq_m_n_f32_s32): Likewise. (vsriq_m_n_s32): Likewise. (vsubq_m_s32): Likewise. (vqshluq_m_n_s32): Likewise. (vabavq_p_s32): Likewise. (vsriq_m_n_u32): Likewise. (vshlq_m_u32): Likewise. (vsubq_m_u32): Likewise. (vabavq_p_u32): Likewise. (vshlq_m_s32): Likewise. (__arm_vsriq_m_n_s8): Define intrinsic. (__arm_vsubq_m_s8): Likewise. (__arm_vqshluq_m_n_s8): Likewise. (__arm_vabavq_p_s8): Likewise. (__arm_vsriq_m_n_u8): Likewise. (__arm_vshlq_m_u8): Likewise. (__arm_vsubq_m_u8): Likewise. (__arm_vabavq_p_u8): Likewise. (__arm_vshlq_m_s8): Likewise. (__arm_vsriq_m_n_s16): Likewise. (__arm_vsubq_m_s16): Likewise. (__arm_vqshluq_m_n_s16): Likewise. (__arm_vabavq_p_s16): Likewise. (__arm_vsriq_m_n_u16): Likewise. (__arm_vshlq_m_u16): Likewise. (__arm_vsubq_m_u16): Likewise. (__arm_vabavq_p_u16): Likewise. (__arm_vshlq_m_s16): Likewise. (__arm_vsriq_m_n_s32): Likewise. (__arm_vsubq_m_s32): Likewise. (__arm_vqshluq_m_n_s32): Likewise. (__arm_vabavq_p_s32): Likewise. (__arm_vsriq_m_n_u32): Likewise. (__arm_vshlq_m_u32): Likewise. (__arm_vsubq_m_u32): Likewise. (__arm_vabavq_p_u32): Likewise. (__arm_vshlq_m_s32): Likewise. (__arm_vcvtq_m_n_f16_u16): Likewise. (__arm_vcvtq_m_n_f16_s16): Likewise. (__arm_vcvtq_m_n_f32_u32): Likewise. (__arm_vcvtq_m_n_f32_s32): Likewise. (vcvtq_m_n): Define polymorphic variant. (vqshluq_m_n): Likewise. (vshlq_m): Likewise. (vsriq_m_n): Likewise. (vsubq_m): Likewise. (vabavq_p): Likewise. * config/arm/arm_mve_builtins.def (QUADOP_UNONE_UNONE_NONE_NONE_UNONE_QUALIFIERS): Use builtin qualifier. (QUADOP_NONE_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise. (QUADOP_NONE_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise. (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise. (QUADOP_UNONE_UNONE_NONE_IMM_UNONE_QUALIFIERS): Likewise. (QUADOP_NONE_NONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise. (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise. (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise. * config/arm/mve.md (VABAVQ_P): Define iterator. (VSHLQ_M): Likewise. (VSRIQ_M_N): Likewise. (VSUBQ_M): Likewise. (VCVTQ_M_N_TO_F): Likewise. (mve_vabavq_p_): Define RTL pattern. (mve_vqshluq_m_n_s): Likewise. (mve_vshlq_m_): Likewise. (mve_vsriq_m_n_): Likewise. (mve_vsubq_m_): Likewise. (mve_vcvtq_m_n_to_f_): Likewise. gcc/testsuite/ChangeLog: 2019-10-29 Andre Vieira Mihail Ionescu Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vabavq_p_s16.c: New test. * gcc.target/arm/mve/intrinsics/vabavq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabavq_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vabavq_p_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vabavq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabavq_p_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshluq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshluq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vshlq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vsubq_m_u8.c: Likewise. ############### Attachment also inlined for ease of reply ############### diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index b0d2a19684dc798e1ae1a4c0496c6c4fddac891d..6dffb36fe179357c62cb4f35d486513971e3487d 100644 --- a/gcc/config/arm/arm-builtins.c +++ b/gcc/config/arm/arm-builtins.c @@ -499,6 +499,62 @@ arm_ternop_none_none_none_none_qualifiers[SIMD_MAX_BUILTIN_ARGS] #define TERNOP_NONE_NONE_NONE_NONE_QUALIFIERS \ (arm_ternop_none_none_none_none_qualifiers) +static enum arm_type_qualifiers +arm_quadop_unone_unone_none_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_unsigned, qualifier_unsigned, qualifier_none, qualifier_none, + qualifier_unsigned }; +#define QUADOP_UNONE_UNONE_NONE_NONE_UNONE_QUALIFIERS \ + (arm_quadop_unone_unone_none_none_unone_qualifiers) + +static enum arm_type_qualifiers +arm_quadop_none_none_none_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_none, qualifier_none, qualifier_none, + qualifier_unsigned }; +#define QUADOP_NONE_NONE_NONE_NONE_UNONE_QUALIFIERS \ + (arm_quadop_none_none_none_none_unone_qualifiers) + +static enum arm_type_qualifiers +arm_quadop_none_none_none_imm_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_none, qualifier_none, qualifier_immediate, + qualifier_unsigned }; +#define QUADOP_NONE_NONE_NONE_IMM_UNONE_QUALIFIERS \ + (arm_quadop_none_none_none_imm_unone_qualifiers) + +static enum arm_type_qualifiers +arm_quadop_unone_unone_unone_unone_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned, + qualifier_unsigned, qualifier_unsigned }; +#define QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE_QUALIFIERS \ + (arm_quadop_unone_unone_unone_unone_unone_qualifiers) + +static enum arm_type_qualifiers +arm_quadop_unone_unone_none_imm_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_unsigned, qualifier_unsigned, qualifier_none, + qualifier_immediate, qualifier_unsigned }; +#define QUADOP_UNONE_UNONE_NONE_IMM_UNONE_QUALIFIERS \ + (arm_quadop_unone_unone_none_imm_unone_qualifiers) + +static enum arm_type_qualifiers +arm_quadop_none_none_unone_imm_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_none, qualifier_unsigned, qualifier_immediate, + qualifier_unsigned }; +#define QUADOP_NONE_NONE_UNONE_IMM_UNONE_QUALIFIERS \ + (arm_quadop_none_none_unone_imm_unone_qualifiers) + +static enum arm_type_qualifiers +arm_quadop_unone_unone_unone_imm_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned, + qualifier_immediate, qualifier_unsigned }; +#define QUADOP_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS \ + (arm_quadop_unone_unone_unone_imm_unone_qualifiers) + +static enum arm_type_qualifiers +arm_quadop_unone_unone_unone_none_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned, + qualifier_none, qualifier_unsigned }; +#define QUADOP_UNONE_UNONE_UNONE_NONE_UNONE_QUALIFIERS \ + (arm_quadop_unone_unone_unone_none_unone_qualifiers) + /* End of Qualifier for MVE builtins. */ /* void ([T element type] *, T, immediate). */ diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index dcb5682ef5c82585889b88ce08c14ddb41e84a3e..8a282966750556f58298a4a7c3a872e2cc7bee51 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -1232,6 +1232,37 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t; #define vqmovnbq_m_u32(__a, __b, __p) __arm_vqmovnbq_m_u32(__a, __b, __p) #define vqmovntq_m_u32(__a, __b, __p) __arm_vqmovntq_m_u32(__a, __b, __p) #define vrev32q_m_u16(__inactive, __a, __p) __arm_vrev32q_m_u16(__inactive, __a, __p) +#define vsriq_m_n_s8(__a, __b, __imm, __p) __arm_vsriq_m_n_s8(__a, __b, __imm, __p) +#define vsubq_m_s8(__inactive, __a, __b, __p) __arm_vsubq_m_s8(__inactive, __a, __b, __p) +#define vcvtq_m_n_f16_u16(__inactive, __a, __imm6, __p) __arm_vcvtq_m_n_f16_u16(__inactive, __a, __imm6, __p) +#define vqshluq_m_n_s8(__inactive, __a, __imm, __p) __arm_vqshluq_m_n_s8(__inactive, __a, __imm, __p) +#define vabavq_p_s8(__a, __b, __c, __p) __arm_vabavq_p_s8(__a, __b, __c, __p) +#define vsriq_m_n_u8(__a, __b, __imm, __p) __arm_vsriq_m_n_u8(__a, __b, __imm, __p) +#define vshlq_m_u8(__inactive, __a, __b, __p) __arm_vshlq_m_u8(__inactive, __a, __b, __p) +#define vsubq_m_u8(__inactive, __a, __b, __p) __arm_vsubq_m_u8(__inactive, __a, __b, __p) +#define vabavq_p_u8(__a, __b, __c, __p) __arm_vabavq_p_u8(__a, __b, __c, __p) +#define vshlq_m_s8(__inactive, __a, __b, __p) __arm_vshlq_m_s8(__inactive, __a, __b, __p) +#define vcvtq_m_n_f16_s16(__inactive, __a, __imm6, __p) __arm_vcvtq_m_n_f16_s16(__inactive, __a, __imm6, __p) +#define vsriq_m_n_s16(__a, __b, __imm, __p) __arm_vsriq_m_n_s16(__a, __b, __imm, __p) +#define vsubq_m_s16(__inactive, __a, __b, __p) __arm_vsubq_m_s16(__inactive, __a, __b, __p) +#define vcvtq_m_n_f32_u32(__inactive, __a, __imm6, __p) __arm_vcvtq_m_n_f32_u32(__inactive, __a, __imm6, __p) +#define vqshluq_m_n_s16(__inactive, __a, __imm, __p) __arm_vqshluq_m_n_s16(__inactive, __a, __imm, __p) +#define vabavq_p_s16(__a, __b, __c, __p) __arm_vabavq_p_s16(__a, __b, __c, __p) +#define vsriq_m_n_u16(__a, __b, __imm, __p) __arm_vsriq_m_n_u16(__a, __b, __imm, __p) +#define vshlq_m_u16(__inactive, __a, __b, __p) __arm_vshlq_m_u16(__inactive, __a, __b, __p) +#define vsubq_m_u16(__inactive, __a, __b, __p) __arm_vsubq_m_u16(__inactive, __a, __b, __p) +#define vabavq_p_u16(__a, __b, __c, __p) __arm_vabavq_p_u16(__a, __b, __c, __p) +#define vshlq_m_s16(__inactive, __a, __b, __p) __arm_vshlq_m_s16(__inactive, __a, __b, __p) +#define vcvtq_m_n_f32_s32(__inactive, __a, __imm6, __p) __arm_vcvtq_m_n_f32_s32(__inactive, __a, __imm6, __p) +#define vsriq_m_n_s32(__a, __b, __imm, __p) __arm_vsriq_m_n_s32(__a, __b, __imm, __p) +#define vsubq_m_s32(__inactive, __a, __b, __p) __arm_vsubq_m_s32(__inactive, __a, __b, __p) +#define vqshluq_m_n_s32(__inactive, __a, __imm, __p) __arm_vqshluq_m_n_s32(__inactive, __a, __imm, __p) +#define vabavq_p_s32(__a, __b, __c, __p) __arm_vabavq_p_s32(__a, __b, __c, __p) +#define vsriq_m_n_u32(__a, __b, __imm, __p) __arm_vsriq_m_n_u32(__a, __b, __imm, __p) +#define vshlq_m_u32(__inactive, __a, __b, __p) __arm_vshlq_m_u32(__inactive, __a, __b, __p) +#define vsubq_m_u32(__inactive, __a, __b, __p) __arm_vsubq_m_u32(__inactive, __a, __b, __p) +#define vabavq_p_u32(__a, __b, __c, __p) __arm_vabavq_p_u32(__a, __b, __c, __p) +#define vshlq_m_s32(__inactive, __a, __b, __p) __arm_vshlq_m_s32(__inactive, __a, __b, __p) #endif __extension__ extern __inline void @@ -7696,6 +7727,196 @@ __arm_vrev32q_m_u16 (uint16x8_t __inactive, uint16x8_t __a, mve_pred16_t __p) { return __builtin_mve_vrev32q_m_uv8hi (__inactive, __a, __p); } + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsriq_m_n_s8 (int8x16_t __a, int8x16_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vsriq_m_n_sv16qi (__a, __b, __imm, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vsubq_m_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshluq_m_n_s8 (uint8x16_t __inactive, int8x16_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vqshluq_m_n_sv16qi (__inactive, __a, __imm, __p); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabavq_p_s8 (uint32_t __a, int8x16_t __b, int8x16_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vabavq_p_sv16qi (__a, __b, __c, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsriq_m_n_u8 (uint8x16_t __a, uint8x16_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vsriq_m_n_uv16qi (__a, __b, __imm, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_m_u8 (uint8x16_t __inactive, uint8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vshlq_m_uv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_m_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vsubq_m_uv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabavq_p_u8 (uint32_t __a, uint8x16_t __b, uint8x16_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vabavq_p_uv16qi (__a, __b, __c, __p); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_m_s8 (int8x16_t __inactive, int8x16_t __a, int8x16_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vshlq_m_sv16qi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsriq_m_n_s16 (int16x8_t __a, int16x8_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vsriq_m_n_sv8hi (__a, __b, __imm, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vsubq_m_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshluq_m_n_s16 (uint16x8_t __inactive, int16x8_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vqshluq_m_n_sv8hi (__inactive, __a, __imm, __p); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabavq_p_s16 (uint32_t __a, int16x8_t __b, int16x8_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vabavq_p_sv8hi (__a, __b, __c, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsriq_m_n_u16 (uint16x8_t __a, uint16x8_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vsriq_m_n_uv8hi (__a, __b, __imm, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vshlq_m_uv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vsubq_m_uv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabavq_p_u16 (uint32_t __a, uint16x8_t __b, uint16x8_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vabavq_p_uv8hi (__a, __b, __c, __p); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_m_s16 (int16x8_t __inactive, int16x8_t __a, int16x8_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vshlq_m_sv8hi (__inactive, __a, __b, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsriq_m_n_s32 (int32x4_t __a, int32x4_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vsriq_m_n_sv4si (__a, __b, __imm, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vsubq_m_sv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqshluq_m_n_s32 (uint32x4_t __inactive, int32x4_t __a, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vqshluq_m_n_sv4si (__inactive, __a, __imm, __p); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabavq_p_s32 (uint32_t __a, int32x4_t __b, int32x4_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vabavq_p_sv4si (__a, __b, __c, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsriq_m_n_u32 (uint32x4_t __a, uint32x4_t __b, const int __imm, mve_pred16_t __p) +{ + return __builtin_mve_vsriq_m_n_uv4si (__a, __b, __imm, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vshlq_m_uv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vsubq_m_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vsubq_m_uv4si (__inactive, __a, __b, __p); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabavq_p_u32 (uint32_t __a, uint32x4_t __b, uint32x4_t __c, mve_pred16_t __p) +{ + return __builtin_mve_vabavq_p_uv4si (__a, __b, __c, __p); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vshlq_m_s32 (int32x4_t __inactive, int32x4_t __a, int32x4_t __b, mve_pred16_t __p) +{ + return __builtin_mve_vshlq_m_sv4si (__inactive, __a, __b, __p); +} + #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ __extension__ extern __inline void @@ -9375,6 +9596,35 @@ __arm_vcvtq_m_u32_f32 (uint32x4_t __inactive, float32x4_t __a, mve_pred16_t __p) { return __builtin_mve_vcvtq_m_from_f_uv4si (__inactive, __a, __p); } + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_m_n_f16_u16 (float16x8_t __inactive, uint16x8_t __a, const int __imm6, mve_pred16_t __p) +{ + return __builtin_mve_vcvtq_m_n_to_f_uv8hf (__inactive, __a, __imm6, __p); +} + +__extension__ extern __inline float16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_m_n_f16_s16 (float16x8_t __inactive, int16x8_t __a, const int __imm6, mve_pred16_t __p) +{ + return __builtin_mve_vcvtq_m_n_to_f_sv8hf (__inactive, __a, __imm6, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_m_n_f32_u32 (float32x4_t __inactive, uint32x4_t __a, const int __imm6, mve_pred16_t __p) +{ + return __builtin_mve_vcvtq_m_n_to_f_uv4sf (__inactive, __a, __imm6, __p); +} + +__extension__ extern __inline float32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtq_m_n_f32_s32 (float32x4_t __inactive, int32x4_t __a, const int __imm6, mve_pred16_t __p) +{ + return __builtin_mve_vcvtq_m_n_to_f_sv4sf (__inactive, __a, __imm6, __p); +} + #endif enum { @@ -10131,6 +10381,15 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcvtq_m_u16_f16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcvtq_m_u32_f32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));}) +#define vcvtq_m_n(p0,p1,p2,p3) __arm_vcvtq_m_n(p0,p1,p2,p3) +#define __arm_vcvtq_m_n(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcvtq_m_n_f16_s16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcvtq_m_n_f32_s32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcvtq_m_n_f16_u16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcvtq_m_n_f32_u32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) + #define vabsq_m(p0,p1,p2) __arm_vabsq_m(p0,p1,p2) #define __arm_vabsq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -10173,19 +10432,6 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmlaq_rot90_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t)), \ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmlaq_rot90_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t)));}) -#define vcmpeqq_m_n(p0,p1,p2) __arm_vcmpeqq_m_n(p0,p1,p2) -#define __arm_vcmpeqq_m_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpeqq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpeqq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpeqq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vcmpeqq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vcmpeqq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t), p2), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vcmpeqq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vcmpeqq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t), p2), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vcmpeqq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t), p2));}) - #define vrndxq_m(p0,p1,p2) __arm_vrndxq_m(p0,p1,p2) #define __arm_vrndxq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -11847,8 +12093,8 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsliq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsliq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) -#define vsriq_n(p0,p1,p2) __arm_vsriq_n(p0,p1,p2) -#define __arm_vsriq_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ +#define vsriq(p0,p1,p2) __arm_vsriq(p0,p1,p2) +#define __arm_vsriq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsriq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ @@ -12169,28 +12415,6 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpcsq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpcsq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) -#define vcmpeqq_m_n(p0,p1,p2) __arm_vcmpeqq_m_n(p0,p1,p2) -#define __arm_vcmpeqq_m_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vcmpeqq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vcmpeqq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vcmpeqq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vcmpeqq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vcmpeqq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t), p2), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vcmpeqq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2));}) - -#define vcmpeqq_m(p0,p1,p2) __arm_vcmpeqq_m(p0,p1,p2) -#define __arm_vcmpeqq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ - __typeof(p1) __p1 = (p1); \ - _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpeqq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpeqq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpeqq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpeqq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpeqq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpeqq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));}) - #define vmladavxq_p(p0,p1,p2) __arm_vmladavxq_p(p0,p1,p2) #define __arm_vmladavxq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -12607,6 +12831,61 @@ extern void *__ARM_undef; #define vrmlsldavhxq_p(p0,p1,p2) __arm_vrmlsldavhxq_p(p0,p1,p2) #define __arm_vrmlsldavhxq_p(p0,p1,p2) __arm_vrmlsldavhxq_p_s32(p0,p1,p2) +#define vqshluq_m_n(p0,p1,p2,p3) __arm_vqshluq_m_n(p0,p1,p2,p3) +#define __arm_vqshluq_m_n(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqshluq_m_n_s8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqshluq_m_n_s16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqshluq_m_n_s32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3));}) + +#define vshlq_m(p0,p1,p2,p3) __arm_vshlq_m(p0,p1,p2,p3) +#define __arm_vshlq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vshlq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vshlq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vshlq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vshlq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vshlq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vshlq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) + +#define vsriq_m(p0,p1,p2,p3) __arm_vsriq_m(p0,p1,p2,p3) +#define __arm_vsriq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsriq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsriq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsriq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2, p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsriq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2, p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsriq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsriq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2, p3));}) + +#define vsubq_m(p0,p1,p2,p3) __arm_vsubq_m(p0,p1,p2,p3) +#define __arm_vsubq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsubq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsubq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsubq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsubq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsubq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsubq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + +#define vabavq_p(p0,p1,p2,p3) __arm_vabavq_p(p0,p1,p2,p3) +#define __arm_vabavq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + __typeof(p2) __p2 = (p2); \ + _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vabavq_p_s8(__p0, __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vabavq_p_s16(__p0, __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vabavq_p_s32(__p0, __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vabavq_p_u8(__p0, __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vabavq_p_u16(__p0, __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vabavq_p_u32(__p0, __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + #endif /* MVE Floating point. */ #ifdef __cplusplus diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def index 4169b31646d4cf55a067131f6b516718c8e970c4..22c3de7c75171e239f2e644308ed3e05d2cdf819 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -502,3 +502,14 @@ VAR1 (TERNOP_NONE_NONE_NONE_UNONE, vaddlvaq_p_s, v4si) VAR1 (TERNOP_NONE_NONE_NONE_NONE, vrmlsldavhaxq_s, v4si) VAR1 (TERNOP_NONE_NONE_NONE_NONE, vrmlsldavhaq_s, v4si) VAR1 (TERNOP_NONE_NONE_NONE_NONE, vrmlaldavhaxq_s, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vsriq_m_n_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vsriq_m_n_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vsubq_m_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vsubq_m_u, v16qi, v8hi, v4si) +VAR2 (QUADOP_NONE_NONE_UNONE_IMM_UNONE, vcvtq_m_n_to_f_u, v8hf, v4sf) +VAR2 (QUADOP_NONE_NONE_NONE_IMM_UNONE, vcvtq_m_n_to_f_s, v8hf, v4sf) +VAR3 (QUADOP_UNONE_UNONE_NONE_IMM_UNONE, vqshluq_m_n_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_NONE_NONE_UNONE, vabavq_p_s, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vabavq_p_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE, vshlq_m_u, v16qi, v8hi, v4si) +VAR3 (QUADOP_NONE_NONE_NONE_NONE_UNONE, vshlq_m_s, v16qi, v8hi, v4si) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 27a12dc533c69372328a7410bda2f68895b4e2bd..0fe7de439a3b40a03299bb2cf668e7cd59f2fc46 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -140,7 +140,10 @@ VCVTPQ_M_S VCVTPQ_M_U VCVTQ_M_N_FROM_F_S VCVTNQ_M_U VREV16Q_M_S VREV16Q_M_U VREV32Q_M VCVTQ_M_FROM_F_U VCVTQ_M_FROM_F_S VRMLALDAVHQ_P_U VADDLVAQ_P_U - VCVTQ_M_N_FROM_F_U]) + VCVTQ_M_N_FROM_F_U VQSHLUQ_M_N_S VABAVQ_P_S + VABAVQ_P_U VSHLQ_M_S VSHLQ_M_U VSRIQ_M_N_S + VSRIQ_M_N_U VSUBQ_M_U VSUBQ_M_S VCVTQ_M_N_TO_F_U + VCVTQ_M_N_TO_F_S]) (define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI") (V4SF "V4SI")]) @@ -244,7 +247,11 @@ (VCVTQ_M_N_FROM_F_U "u") (VCVTQ_M_FROM_F_S "s") (VCVTQ_M_FROM_F_U "u") (VRMLALDAVHQ_P_U "u") (VRMLALDAVHQ_P_S "s") (VADDLVAQ_P_U "u") - (VCVTQ_M_N_FROM_F_S "s")]) + (VCVTQ_M_N_FROM_F_S "s") (VABAVQ_P_U "u") + (VABAVQ_P_S "s") (VSHLQ_M_S "s") (VSHLQ_M_U "u") + (VSRIQ_M_N_S "s") (VSRIQ_M_N_U "u") (VSUBQ_M_S "s") + (VSUBQ_M_U "u") (VCVTQ_M_N_TO_F_S "s") + (VCVTQ_M_N_TO_F_U "u")]) (define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32") (VCTP64Q "64") (VCTP8Q_M "8") (VCTP16Q_M "16") @@ -407,6 +414,11 @@ (define_int_iterator VCVTQ_M_FROM_F [VCVTQ_M_FROM_F_U VCVTQ_M_FROM_F_S]) (define_int_iterator VRMLALDAVHQ_P [VRMLALDAVHQ_P_S VRMLALDAVHQ_P_U]) (define_int_iterator VADDLVAQ_P [VADDLVAQ_P_U VADDLVAQ_P_S]) +(define_int_iterator VABAVQ_P [VABAVQ_P_S VABAVQ_P_U]) +(define_int_iterator VSHLQ_M [VSHLQ_M_S VSHLQ_M_U]) +(define_int_iterator VSRIQ_M_N [VSRIQ_M_N_S VSRIQ_M_N_U]) +(define_int_iterator VSUBQ_M [VSUBQ_M_U VSUBQ_M_S]) +(define_int_iterator VCVTQ_M_N_TO_F [VCVTQ_M_N_TO_F_U VCVTQ_M_N_TO_F_S]) (define_insn "*mve_mov" [(set (match_operand:MVE_types 0 "s_register_operand" "=w,w,r,w,w,r,w") @@ -5544,7 +5556,7 @@ VSHRNTQ_N)) ] "TARGET_HAVE_MVE" - "vshrnt.i%# %q0, %q2, %3" + "vshrnt.i%#\t%q0, %q2, %3" [(set_attr "type" "mve_move") ]) @@ -5560,7 +5572,7 @@ VCVTMQ_M)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vcvtmt.%#.f%# %q0, %q2" + "vpst\;vcvtmt.%#.f%#\t%q0, %q2" [(set_attr "type" "mve_move") (set_attr "length""8")]) @@ -5576,7 +5588,7 @@ VCVTPQ_M)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vcvtpt.%#.f%# %q0, %q2" + "vpst\;vcvtpt.%#.f%#\t%q0, %q2" [(set_attr "type" "mve_move") (set_attr "length""8")]) @@ -5592,7 +5604,7 @@ VCVTNQ_M)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vcvtnt.%#.f%# %q0, %q2" + "vpst\;vcvtnt.%#.f%#\t%q0, %q2" [(set_attr "type" "mve_move") (set_attr "length""8")]) @@ -5609,7 +5621,7 @@ VCVTQ_M_N_FROM_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vcvtt.%#.f%# %q0, %q2, %3" + "vpst\;vcvtt.%#.f%#\t%q0, %q2, %3" [(set_attr "type" "mve_move") (set_attr "length""8")]) @@ -5641,7 +5653,7 @@ VCVTQ_M_FROM_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vcvtt.%#.f%# %q0, %q2" + "vpst\;vcvtt.%#.f%#\t%q0, %q2" [(set_attr "type" "mve_move") (set_attr "length""8")]) @@ -5676,3 +5688,101 @@ "vrmlsldavha.s32 %Q0, %R0, %q2, %q3" [(set_attr "type" "mve_move") ]) + +;; +;; [vabavq_p_s, vabavq_p_u]) +;; +(define_insn "mve_vabavq_p_" + [ + (set (match_operand:SI 0 "s_register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VABAVQ_P)) + ] + "TARGET_HAVE_MVE" + "vpst\;vabavt.%#\t%0, %q2, %q3" + [(set_attr "type" "mve_move") +]) + +;; +;; [vqshluq_m_n_s]) +;; +(define_insn "mve_vqshluq_m_n_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:SI 3 "mve_imm_7" "Ra") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VQSHLUQ_M_N_S)) + ] + "TARGET_HAVE_MVE" + "vpst\n\tvqshlut.s%#\t%q0, %q2, %3" + [(set_attr "type" "mve_move")]) + +;; +;; [vshlq_m_s, vshlq_m_u]) +;; +(define_insn "mve_vshlq_m_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VSHLQ_M)) + ] + "TARGET_HAVE_MVE" + "vpst\;vshlt.%#\t%q0, %q2, %q3" + [(set_attr "type" "mve_move")]) + +;; +;; [vsriq_m_n_s, vsriq_m_n_u]) +;; +(define_insn "mve_vsriq_m_n_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:SI 3 "mve_imm_selective_upto_8" "Rg") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VSRIQ_M_N)) + ] + "TARGET_HAVE_MVE" + "vpst\;vsrit.%#\t%q0, %q2, %3" + [(set_attr "type" "mve_move")]) + +;; +;; [vsubq_m_u, vsubq_m_s]) +;; +(define_insn "mve_vsubq_m_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") + (match_operand:MVE_2 2 "s_register_operand" "w") + (match_operand:MVE_2 3 "s_register_operand" "w") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VSUBQ_M)) + ] + "TARGET_HAVE_MVE" + "vpst\;vsubt.i%#\t%q0, %q2, %q3" + [(set_attr "type" "mve_move")]) + +;; +;; [vcvtq_m_n_to_f_u, vcvtq_m_n_to_f_s]) +;; +(define_insn "mve_vcvtq_m_n_to_f_" + [ + (set (match_operand:MVE_0 0 "s_register_operand" "=w") + (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") + (match_operand: 2 "s_register_operand" "w") + (match_operand:SI 3 "mve_imm_16" "Rd") + (match_operand:HI 4 "vpr_register_operand" "Up")] + VCVTQ_M_N_TO_F)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vpst\;vcvtt.f%#.%#\t%q0, %q2, %3" + [(set_attr "type" "mve_move") + (set_attr "length""8")]) diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s16.c new file mode 100644 index 0000000000000000000000000000000000000000..0c67c3afabb3780d6dcb4082a822389d868551f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s16.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +uint32_t +foo (uint32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) +{ + return vabavq_p_s16 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vabavt.s16" } } */ + +uint32_t +foo1 (uint32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) +{ + return vabavq_p (a, b, c, p); +} + +/* { dg-final { scan-assembler "vabavt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s32.c new file mode 100644 index 0000000000000000000000000000000000000000..4a8c8425208e77295464e7b0a26bfd194170388f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s32.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +uint32_t +foo (uint32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) +{ + return vabavq_p_s32 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vabavt.s32" } } */ + +uint32_t +foo1 (uint32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) +{ + return vabavq_p (a, b, c, p); +} + +/* { dg-final { scan-assembler "vabavt.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s8.c new file mode 100644 index 0000000000000000000000000000000000000000..80f09cbd4b17ae11ab88c69af579cfe0789c7b9e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s8.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +uint32_t +foo (uint32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p) +{ + return vabavq_p_s8 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vabavt.s8" } } */ + +uint32_t +foo1 (uint32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p) +{ + return vabavq_p (a, b, c, p); +} + +/* { dg-final { scan-assembler "vabavt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u16.c new file mode 100644 index 0000000000000000000000000000000000000000..959bc7c3eb16e1937be8d88da6d38c4b93d11adb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u16.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +uint32_t +foo (uint32_t a, uint16x8_t b, uint16x8_t c, mve_pred16_t p) +{ + return vabavq_p_u16 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vabavt.u16" } } */ + +uint32_t +foo1 (uint32_t a, uint16x8_t b, uint16x8_t c, mve_pred16_t p) +{ + return vabavq_p (a, b, c, p); +} + +/* { dg-final { scan-assembler "vabavt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u32.c new file mode 100644 index 0000000000000000000000000000000000000000..7f32cb521ff1686c7eb68612c90c45f319ef2a81 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u32.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +uint32_t +foo (uint32_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p) +{ + return vabavq_p_u32 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vabavt.u32" } } */ + +uint32_t +foo1 (uint32_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p) +{ + return vabavq_p (a, b, c, p); +} + +/* { dg-final { scan-assembler "vabavt.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u8.c new file mode 100644 index 0000000000000000000000000000000000000000..7654e36f1d17e05018399a77ce2e60efe532dd1e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u8.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +uint32_t +foo (uint32_t a, uint8x16_t b, uint8x16_t c, mve_pred16_t p) +{ + return vabavq_p_u8 (a, b, c, p); +} + +/* { dg-final { scan-assembler "vabavt.u8" } } */ + +uint32_t +foo1 (uint32_t a, uint8x16_t b, uint8x16_t c, mve_pred16_t p) +{ + return vabavq_p (a, b, c, p); +} + +/* { dg-final { scan-assembler "vabavt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16.c index b40247d3ee40e491ae304b0cd4a8d656af1cc2cc..2db6c1369a8b238ce02c73b397d60e5d713786e3 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16.c @@ -16,7 +16,7 @@ foo (float16x8_t a, float16_t b, mve_pred16_t p) mve_pred16_t foo1 (float16x8_t a, float16_t b, mve_pred16_t p) { - return vcmpeqq_m_n (a, b, p); + return vcmpeqq_m (a, b, p); } /* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32.c index 9b9ecf8c5518fdef76def0c75a87a1246974733b..e3a19aa7ae6dee749c7f6d839a068f458771fcaa 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32.c @@ -16,7 +16,7 @@ foo (float32x4_t a, float32_t b, mve_pred16_t p) mve_pred16_t foo1 (float32x4_t a, float32_t b, mve_pred16_t p) { - return vcmpeqq_m_n (a, b, p); + return vcmpeqq_m (a, b, p); } /* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s16.c index b510d453b05ffc38ee26184c92d6083a39403b36..2c12d25e2c9392280eeaab5f2324e7a969805e1c 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s16.c @@ -16,7 +16,7 @@ foo (int16x8_t a, int16_t b, mve_pred16_t p) mve_pred16_t foo1 (int16x8_t a, int16_t b, mve_pred16_t p) { - return vcmpeqq_m_n (a, b, p); + return vcmpeqq_m (a, b, p); } /* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s32.c index 239273dbf080f4f072d8c28ed0a2a72f2610ce43..ae9d2097500e03868051674cf4293069c70fcf96 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s32.c @@ -16,7 +16,7 @@ foo (int32x4_t a, int32_t b, mve_pred16_t p) mve_pred16_t foo1 (int32x4_t a, int32_t b, mve_pred16_t p) { - return vcmpeqq_m_n (a, b, p); + return vcmpeqq_m (a, b, p); } /* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c index 2d811e6f0efdf4a313c26a9e0c6aa1a297b3d3cd..3b55515e604a544d9ad4034f3b4fdec1d6d57bd5 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c @@ -16,7 +16,7 @@ foo (int8x16_t a, int8_t b, mve_pred16_t p) mve_pred16_t foo1 (int8x16_t a, int8_t b, mve_pred16_t p) { - return vcmpeqq_m_n (a, b, p); + return vcmpeqq_m (a, b, p); } /* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u16.c index fd0867387de694933ff487d16d16627d79a0cacc..a56ecb5df0a5363d694e4c2fef44152579642fbd 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u16.c @@ -16,7 +16,7 @@ foo (uint16x8_t a, uint16_t b, mve_pred16_t p) mve_pred16_t foo1 (uint16x8_t a, uint16_t b, mve_pred16_t p) { - return vcmpeqq_m_n (a, b, p); + return vcmpeqq_m (a, b, p); } /* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u32.c index f56f37e3088f286118862024a9dba2aea4a5db2d..c9f90b8a4c1a4540ed05af9690599b4ea8a38904 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u32.c @@ -16,7 +16,7 @@ foo (uint32x4_t a, uint32_t b, mve_pred16_t p) mve_pred16_t foo1 (uint32x4_t a, uint32_t b, mve_pred16_t p) { - return vcmpeqq_m_n (a, b, p); + return vcmpeqq_m (a, b, p); } /* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c index 0178fe39e2b5a2cf77b4818f2c096779ed7bb6a7..6f2792496c6b22be7c114092a3c4a8f27b6de780 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c @@ -16,7 +16,7 @@ foo (uint8x16_t a, uint8_t b, mve_pred16_t p) mve_pred16_t foo1 (uint8x16_t a, uint8_t b, mve_pred16_t p) { - return vcmpeqq_m_n (a, b, p); + return vcmpeqq_m (a, b, p); } /* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_s16.c new file mode 100644 index 0000000000000000000000000000000000000000..df72d22479b69a0db2b4596182fd7b2ca656218c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_s16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t inactive, int16x8_t a, mve_pred16_t p) +{ + return vcvtq_m_n_f16_s16 (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.f16.s16" } } */ + +float16x8_t +foo1 (float16x8_t inactive, int16x8_t a, mve_pred16_t p) +{ + return vcvtq_m_n (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.f16.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_u16.c new file mode 100644 index 0000000000000000000000000000000000000000..ad7cf0725c7c7ee53fb0f5e4e50a29a09c91b57c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f16_u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +float16x8_t +foo (float16x8_t inactive, uint16x8_t a, mve_pred16_t p) +{ + return vcvtq_m_n_f16_u16 (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.f16.u16" } } */ + +float16x8_t +foo1 (float16x8_t inactive, uint16x8_t a, mve_pred16_t p) +{ + return vcvtq_m_n (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.f16.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_s32.c new file mode 100644 index 0000000000000000000000000000000000000000..a90bf1a163ec721b13c2af19b1eda27b5c6f7f48 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_s32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t inactive, int32x4_t a, mve_pred16_t p) +{ + return vcvtq_m_n_f32_s32 (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.f32.s32" } } */ + +float32x4_t +foo1 (float32x4_t inactive, int32x4_t a, mve_pred16_t p) +{ + return vcvtq_m_n (inactive, a, 1, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.f32.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_u32.c new file mode 100644 index 0000000000000000000000000000000000000000..3581481ffd9db52dc027793a32dc2e1dc6125ced --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_n_f32_u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve.fp -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +float32x4_t +foo (float32x4_t inactive, uint32x4_t a, mve_pred16_t p) +{ + return vcvtq_m_n_f32_u32 (inactive, a, 16, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.f32.u32" } } */ + +float32x4_t +foo1 (float32x4_t inactive, uint32x4_t a, mve_pred16_t p) +{ + return vcvtq_m_n (inactive, a, 16, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vcvtt.f32.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s16.c new file mode 100644 index 0000000000000000000000000000000000000000..71115723d4b051ba977a4c89b086efd376e779a8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, int16x8_t a, mve_pred16_t p) +{ + return vqshluq_m_n_s16 (inactive, a, 7, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshlut.s16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, int16x8_t a, mve_pred16_t p) +{ + return vqshluq_m_n (inactive, a, 7, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s32.c new file mode 100644 index 0000000000000000000000000000000000000000..60684f8d755f60a866b2e49ab3fc0e4fa11220fc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, int32x4_t a, mve_pred16_t p) +{ + return vqshluq_m_n_s32 (inactive, a, 7, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshlut.s32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, int32x4_t a, mve_pred16_t p) +{ + return vqshluq_m_n (inactive, a, 7, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c new file mode 100644 index 0000000000000000000000000000000000000000..53f0c67660d0def94807a3d91ad8fb50fda5eb02 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, int8x16_t a, mve_pred16_t p) +{ + return vqshluq_m_n_s8 (inactive, a, 7, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vqshlut.s8" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, int8x16_t a, mve_pred16_t p) +{ + return vqshluq_m_n (inactive, a, 7, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s16.c new file mode 100644 index 0000000000000000000000000000000000000000..cb412e4dcb6993cf23b39a9668720bab1b96c357 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vshlq_m_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlt.s16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vshlq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s32.c new file mode 100644 index 0000000000000000000000000000000000000000..a356b02b0741aa0c0801ee219194db99c49322dc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vshlq_m_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlt.s32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vshlq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s8.c new file mode 100644 index 0000000000000000000000000000000000000000..57b81d2a6ab7f7755c750c8e0e3d7dc126b445ef --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vshlq_m_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlt.s8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vshlq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u16.c new file mode 100644 index 0000000000000000000000000000000000000000..31baa5a1b68e149695db130262411e0a7854033e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vshlq_m_u16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlt.u16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vshlq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u32.c new file mode 100644 index 0000000000000000000000000000000000000000..e4b547c68fc7c676df40416bd0771aef13c6bec2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vshlq_m_u32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlt.u32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vshlq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u8.c new file mode 100644 index 0000000000000000000000000000000000000000..9905fa6fccac2286ae94ff4354dcf014321568c2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vshlq_m_u8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vshlt.u8" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vshlq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c new file mode 100644 index 0000000000000000000000000000000000000000..0f707c0d05ffcfab8520f564066915eae3efd9ac --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vsriq_m_n_s16 (a, b, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsrit.16" } } */ + +int16x8_t +foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vsriq_m (a, b, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c new file mode 100644 index 0000000000000000000000000000000000000000..d0d29363c3786ff7e47650d39dbca65c3e5fb558 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vsriq_m_n_s32 (a, b, 2, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsrit.32" } } */ + +int32x4_t +foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vsriq_m (a, b, 2, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c new file mode 100644 index 0000000000000000000000000000000000000000..cab82024c36c0cc3062daa736084130bc12a8f44 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vsriq_m_n_s8 (a, b, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsrit.8" } } */ + +int8x16_t +foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vsriq_m (a, b, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c new file mode 100644 index 0000000000000000000000000000000000000000..bccc3e9279d850b84e6d20bb31c7a9e98f7a2624 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vsriq_m_n_u16 (a, b, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsrit.16" } } */ + +uint16x8_t +foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vsriq_m (a, b, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c new file mode 100644 index 0000000000000000000000000000000000000000..d81835ff5db9b679c84ccea9e045a421d85dfd13 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vsriq_m_n_u32 (a, b, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsrit.32" } } */ + +uint32x4_t +foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vsriq_m (a, b, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c new file mode 100644 index 0000000000000000000000000000000000000000..4327d6e101ce3e4fa0ccc1f5bf7af2ceb77b8dfe --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vsriq_m_n_u8 (a, b, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsrit.8" } } */ + +uint8x16_t +foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vsriq_m (a, b, 4, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s16.c index fca14b89661ffcd133a818070958243985add8df..00828e3ce74ed31f05ce86a21e430a27211dd024 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s16.c @@ -15,7 +15,7 @@ foo (int16x8_t a, int16x8_t b) int16x8_t foo1 (int16x8_t a, int16x8_t b) { - return vsriq_n (a, b, 4); + return vsriq (a, b, 4); } /* { dg-final { scan-assembler "vsri.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s32.c index 55ef218fcc6995b661946dbfc894225260125157..03060c33e663ee6f596270768ce34712493330d6 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s32.c @@ -15,7 +15,7 @@ foo (int32x4_t a, int32x4_t b) int32x4_t foo1 (int32x4_t a, int32x4_t b) { - return vsriq_n (a, b, 4); + return vsriq (a, b, 4); } /* { dg-final { scan-assembler "vsri.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s8.c index 83d726c2806f2547c886472e4ebd048aa80c61a2..e489cef12817a8a05b041646ad3e6b16a565468a 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_s8.c @@ -15,7 +15,7 @@ foo (int8x16_t a, int8x16_t b) int8x16_t foo1 (int8x16_t a, int8x16_t b) { - return vsriq_n (a, b, 4); + return vsriq (a, b, 4); } /* { dg-final { scan-assembler "vsri.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u16.c index 6b49b46f6af78d16a4d281d07b4a00da5fb8a1e0..28f2558ce51d39e17c6b846ad23028839859a9f5 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u16.c @@ -15,7 +15,7 @@ foo (uint16x8_t a, uint16x8_t b) uint16x8_t foo1 (uint16x8_t a, uint16x8_t b) { - return vsriq_n (a, b, 4); + return vsriq (a, b, 4); } /* { dg-final { scan-assembler "vsri.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u32.c index 9849355f5c32f59589fa69b868550f88f4e2ec2f..54ef642b9d8180589f9f9ad8fe2731f131c99759 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u32.c @@ -15,7 +15,7 @@ foo (uint32x4_t a, uint32x4_t b) uint32x4_t foo1 (uint32x4_t a, uint32x4_t b) { - return vsriq_n (a, b, 4); + return vsriq (a, b, 4); } /* { dg-final { scan-assembler "vsri.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u8.c index 271248f7fa48372bf11233fa118a05b663a9b278..ee453ddbfd555a0d342aa1080d1ae0f2457032a5 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsriq_n_u8.c @@ -15,7 +15,7 @@ foo (uint8x16_t a, uint8x16_t b) uint8x16_t foo1 (uint8x16_t a, uint8x16_t b) { - return vsriq_n (a, b, 4); + return vsriq (a, b, 4); } /* { dg-final { scan-assembler "vsri.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s16.c new file mode 100644 index 0000000000000000000000000000000000000000..4937ee3187eec987a4c3f0048037325a46e2e3c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vsubq_m_s16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsubt.i16" } } */ + +int16x8_t +foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ + return vsubq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s32.c new file mode 100644 index 0000000000000000000000000000000000000000..52c6144d2a022a84ca6d64fc4628b6da036457c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vsubq_m_s32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsubt.i32" } } */ + +int32x4_t +foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ + return vsubq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s8.c new file mode 100644 index 0000000000000000000000000000000000000000..c4e88154369b60f3427d8ca4195d33a73d663e38 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vsubq_m_s8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsubt.i8" } } */ + +int8x16_t +foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ + return vsubq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u16.c new file mode 100644 index 0000000000000000000000000000000000000000..43ef332c487fb7a97cc2b1b3a396e5a6e3e77b26 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vsubq_m_u16 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsubt.i16" } } */ + +uint16x8_t +foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) +{ + return vsubq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u32.c new file mode 100644 index 0000000000000000000000000000000000000000..ab081b4e71106901b4ea677df7c0a7cb4c6d6444 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vsubq_m_u32 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsubt.i32" } } */ + +uint32x4_t +foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) +{ + return vsubq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u8.c new file mode 100644 index 0000000000000000000000000000000000000000..bb7ffc1f6bfd65dc05946c8de1632239f9c16aea --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_m_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vsubq_m_u8 (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler "vsubt.i8" } } */ + +uint8x16_t +foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) +{ + return vsubq_m (inactive, a, b, p); +} + +/* { dg-final { scan-assembler "vpst" } } */