@@ -738,6 +738,26 @@ arm_strsbwbu_p_qualifiers[SIMD_MAX_BUILTIN_ARGS]
qualifier_unsigned, qualifier_unsigned};
#define STRSBWBU_P_QUALIFIERS (arm_strsbwbu_p_qualifiers)
+static enum arm_type_qualifiers
+arm_lsll_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+ = { qualifier_unsigned, qualifier_unsigned, qualifier_none};
+#define LSLL_QUALIFIERS (arm_lsll_qualifiers)
+
+static enum arm_type_qualifiers
+arm_uqshl_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+ = { qualifier_unsigned, qualifier_unsigned, qualifier_const};
+#define UQSHL_QUALIFIERS (arm_uqshl_qualifiers)
+
+static enum arm_type_qualifiers
+arm_asrl_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+ = { qualifier_none, qualifier_none, qualifier_none};
+#define ASRL_QUALIFIERS (arm_asrl_qualifiers)
+
+static enum arm_type_qualifiers
+arm_sqshl_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+ = { qualifier_unsigned, qualifier_unsigned, qualifier_const};
+#define SQSHL_QUALIFIERS (arm_sqshl_qualifiers)
+
/* End of Qualifier for MVE builtins. */
/* void ([T element type] *, T, immediate). */
@@ -2526,6 +2526,22 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t;
#define vgetq_lane_u16(__a, __idx) __arm_vgetq_lane_u16(__a, __idx)
#define vgetq_lane_u32(__a, __idx) __arm_vgetq_lane_u32(__a, __idx)
#define vgetq_lane_u64(__a, __idx) __arm_vgetq_lane_u64(__a, __idx)
+#define sqrshr(__p0, __p1) __arm_sqrshr(__p0, __p1)
+#define sqrshrl(__p0, __p1) __arm_sqrshrl(__p0, __p1)
+#define sqrshrl_sat48(__p0, __p1) __arm_sqrshrl_sat48(__p0, __p1)
+#define sqshl(__p0, __p1) __arm_sqshl(__p0, __p1)
+#define sqshll(__p0, __p1) __arm_sqshll(__p0, __p1)
+#define srshr(__p0, __p1) __arm_srshr(__p0, __p1)
+#define srshrl(__p0, __p1) __arm_srshrl(__p0, __p1)
+#define uqrshl(__p0, __p1) __arm_uqrshl(__p0, __p1)
+#define uqrshll(__p0, __p1) __arm_uqrshll(__p0, __p1)
+#define uqrshll_sat48(__p0, __p1) __arm_uqrshll_sat48(__p0, __p1)
+#define uqshl(__p0, __p1) __arm_uqshl(__p0, __p1)
+#define uqshll(__p0, __p1) __arm_uqshll(__p0, __p1)
+#define urshr(__p0, __p1) __arm_urshr(__p0, __p1)
+#define urshrl(__p0, __p1) __arm_urshrl(__p0, __p1)
+#define lsll(__p0, __p1) __arm_lsll(__p0, __p1)
+#define asrl(__p0, __p1) __arm_asrl(__p0, __p1)
#endif
/* For big-endian, GCC's vector indices are reversed within each 64 bits
@@ -16539,6 +16555,118 @@ __arm_vgetq_lane_u64 (uint64x2_t __a, const int __idx)
return __a[__ARM_LANEQ(__a,__idx)];
}
+__extension__ extern __inline uint64_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_lsll (uint64_t value, int32_t shift)
+{
+ return (value << shift);
+}
+
+__extension__ extern __inline int64_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_asrl (int64_t value, int32_t shift)
+{
+ return (value >> shift);
+}
+
+__extension__ extern __inline uint64_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_uqrshll (uint64_t value, int32_t shift)
+{
+ return __builtin_mve_uqrshll_sat64_di (value, shift);
+}
+
+__extension__ extern __inline uint64_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_uqrshll_sat48 (uint64_t value, int32_t shift)
+{
+ return __builtin_mve_uqrshll_sat48_di (value, shift);
+}
+
+__extension__ extern __inline int64_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_sqrshrl (int64_t value, int32_t shift)
+{
+ return __builtin_mve_sqrshrl_sat64_di (value, shift);
+}
+
+__extension__ extern __inline int64_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_sqrshrl_sat48 (int64_t value, int32_t shift)
+{
+ return __builtin_mve_sqrshrl_sat48_di (value, shift);
+}
+
+__extension__ extern __inline uint64_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_uqshll (uint64_t value, const int shift)
+{
+ return __builtin_mve_uqshll_di (value, shift);
+}
+
+__extension__ extern __inline uint64_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_urshrl (uint64_t value, const int shift)
+{
+ return __builtin_mve_urshrl_di (value, shift);
+}
+
+__extension__ extern __inline int64_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_srshrl (int64_t value, const int shift)
+{
+ return __builtin_mve_srshrl_di (value, shift);
+}
+
+__extension__ extern __inline int64_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_sqshll (int64_t value, const int shift)
+{
+ return __builtin_mve_sqshll_di (value, shift);
+}
+
+__extension__ extern __inline uint32_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_uqrshl (uint32_t value, int32_t shift)
+{
+ return __builtin_mve_uqrshl_si (value, shift);
+}
+
+__extension__ extern __inline int32_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_sqrshr (int32_t value, int32_t shift)
+{
+ return __builtin_mve_sqrshr_si (value, shift);
+}
+
+__extension__ extern __inline uint32_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_uqshl (uint32_t value, const int shift)
+{
+ return __builtin_mve_uqshl_si (value, shift);
+}
+
+__extension__ extern __inline uint32_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_urshr (uint32_t value, const int shift)
+{
+ return __builtin_mve_urshr_si (value, shift);
+}
+
+__extension__ extern __inline int32_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_sqshl (int32_t value, const int shift)
+{
+ return __builtin_mve_sqshl_si (value, shift);
+}
+
+__extension__ extern __inline int32_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_srshr (int32_t value, const int shift)
+{
+ return __builtin_mve_srshr_si (value, shift);
+}
+
#if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */
__extension__ extern __inline void
@@ -876,3 +876,17 @@ VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vsbcq_m_u, v4si)
VAR5 (STORE1, vst2q, v16qi, v8hi, v4si, v8hf, v4sf)
VAR5 (LOAD1, vld4q, v16qi, v8hi, v4si, v8hf, v4sf)
VAR5 (LOAD1, vld2q, v16qi, v8hi, v4si, v8hf, v4sf)
+VAR1 (ASRL, sqrshr_,si)
+VAR1 (ASRL, sqrshrl_sat64_,di)
+VAR1 (ASRL, sqrshrl_sat48_,di)
+VAR1 (LSLL, uqrshl_, si)
+VAR1 (LSLL, uqrshll_sat64_, di)
+VAR1 (LSLL, uqrshll_sat48_, di)
+VAR1 (SQSHL,srshr_,si)
+VAR1 (SQSHL,srshrl_,di)
+VAR1 (SQSHL,sqshl_,si)
+VAR1 (SQSHL,sqshll_,di)
+VAR1 (UQSHL, urshr_, si)
+VAR1 (UQSHL, urshrl_, di)
+VAR1 (UQSHL, uqshl_, si)
+VAR1 (UQSHL, uqshll_, di)
@@ -214,7 +214,9 @@
VLDRDQGBWB_S VLDRDQGBWB_U VADCQ_U VADCQ_M_U VADCQ_S
VADCQ_M_S VSBCIQ_U VSBCIQ_S VSBCIQ_M_U VSBCIQ_M_S
VSBCQ_U VSBCQ_S VSBCQ_M_U VSBCQ_M_S VADCIQ_U VADCIQ_M_U
- VADCIQ_S VADCIQ_M_S VLD2Q VLD4Q VST2Q])
+ VADCIQ_S VADCIQ_M_S VLD2Q VLD4Q VST2Q SRSHRL SRSHR
+ URSHR URSHRL SQRSHR UQRSHL UQRSHLL_64
+ UQRSHLL_48 SQRSHRL_64 SQRSHRL_48])
(define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI")
(V4SF "V4SI")])
@@ -391,7 +393,8 @@
(VSBCIQ_M_U "u") (VSBCIQ_S "s") (VSBCIQ_M_S "s")
(VADCQ_U "u") (VADCQ_M_U "u") (VADCQ_S "s")
(VADCIQ_U "u") (VADCIQ_M_U "u") (VADCIQ_S "s")
- (VADCIQ_M_S "s")])
+ (VADCIQ_M_S "s") (SQRSHRL_64 "64") (SQRSHRL_48 "48")
+ (UQRSHLL_64 "64") (UQRSHLL_48 "48")])
(define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32")
(VCTP64Q "64") (VCTP8Q_M "8") (VCTP16Q_M "16")
@@ -654,7 +657,8 @@
(define_int_iterator VSBCIQ_M [VSBCIQ_M_U VSBCIQ_M_S])
(define_int_iterator VADCQ [VADCQ_U VADCQ_S])
(define_int_iterator VADCQ_M [VADCQ_M_U VADCQ_M_S])
-
+(define_int_iterator UQRSHLLQ [UQRSHLL_64 UQRSHLL_48])
+(define_int_iterator SQRSHRLQ [SQRSHRL_64 SQRSHRL_48])
(define_insn "*mve_mov<mode>"
[(set (match_operand:MVE_types 0 "s_register_operand" "=w,w,r,w,w,r,w")
@@ -10983,3 +10987,143 @@
return "vmov\t%f0, %J1, %K1";
}
[(set_attr "type" "mve_move")])
+
+;;
+;; [uqrshll_di]
+;;
+(define_insn "mve_uqrshll_sat<supf>_di"
+ [(set (match_operand:DI 0 "arm_general_register_operand" "+r")
+ (unspec:DI [(match_operand:DI 1 "arm_general_register_operand" "r")
+ (match_operand:SI 2 "s_register_operand" "r")]
+ UQRSHLLQ))]
+ "TARGET_HAVE_MVE"
+ "uqrshll%?\\t%Q1, %R1, #<supf>, %2"
+ [(set_attr "predicable" "yes")])
+
+;;
+;; [sqrshrl_di]
+;;
+(define_insn "mve_sqrshrl_sat<supf>_di"
+ [(set (match_operand:DI 0 "arm_general_register_operand" "+r")
+ (unspec:DI [(match_operand:DI 1 "arm_general_register_operand" "r")
+ (match_operand:SI 2 "s_register_operand" "r")]
+ SQRSHRLQ))]
+ "TARGET_HAVE_MVE"
+ "sqrshrl%?\\t%Q1, %R1, #<supf>, %2"
+ [(set_attr "predicable" "yes")])
+
+;;
+;; [uqrshl_si]
+;;
+(define_insn "mve_uqrshl_si"
+ [(set (match_operand:SI 0 "arm_general_register_operand" "+r")
+ (unspec:SI [(match_operand:SI 1 "arm_general_register_operand" "r")
+ (match_operand:SI 2 "s_register_operand" "r")]
+ UQRSHL))]
+ "TARGET_HAVE_MVE"
+ "uqrshl%?\\t%1, %2"
+ [(set_attr "predicable" "yes")])
+
+;;
+;; [sqrshr_si]
+;;
+(define_insn "mve_sqrshr_si"
+ [(set (match_operand:SI 0 "arm_general_register_operand" "+r")
+ (unspec:SI [(match_operand:SI 1 "arm_general_register_operand" "r")
+ (match_operand:SI 2 "s_register_operand" "r")]
+ SQRSHR))]
+ "TARGET_HAVE_MVE"
+ "sqrshr%?\\t%1, %2"
+ [(set_attr "predicable" "yes")])
+
+;;
+;; [uqshll_di]
+;;
+(define_insn "mve_uqshll_di"
+ [(set (match_operand:DI 0 "arm_general_register_operand" "+r")
+ (us_ashift:DI (match_operand:DI 1 "arm_general_register_operand" "r")
+ (match_operand:SI 2 "arm_reg_or_long_shift_imm" "rPg")))]
+ "TARGET_HAVE_MVE"
+ "uqshll%?\\t%Q1, %R1, %2"
+ [(set_attr "predicable" "yes")])
+
+;;
+;; [urshrl_di]
+;;
+(define_insn "mve_urshrl_di"
+ [(set (match_operand:DI 0 "arm_general_register_operand" "+r")
+ (unspec:DI [(match_operand:DI 1 "arm_general_register_operand" "r")
+ (match_operand:SI 2 "arm_reg_or_long_shift_imm" "rPg")]
+ URSHRL))]
+ "TARGET_HAVE_MVE"
+ "urshrl%?\\t%Q1, %R1, %2"
+ [(set_attr "predicable" "yes")])
+
+;;
+;; [uqshl_si]
+;;
+(define_insn "mve_uqshl_si"
+ [(set (match_operand:SI 0 "arm_general_register_operand" "+r")
+ (us_ashift:SI (match_operand:SI 1 "arm_general_register_operand" "r")
+ (match_operand:SI 2 "arm_reg_or_long_shift_imm" "rPg")))]
+ "TARGET_HAVE_MVE"
+ "uqshl%?\\t%1, %2"
+ [(set_attr "predicable" "yes")])
+
+;;
+;; [urshr_si]
+;;
+(define_insn "mve_urshr_si"
+ [(set (match_operand:SI 0 "arm_general_register_operand" "+r")
+ (unspec:SI [(match_operand:SI 1 "arm_general_register_operand" "r")
+ (match_operand:SI 2 "arm_reg_or_long_shift_imm" "rPg")]
+ URSHR))]
+ "TARGET_HAVE_MVE"
+ "urshr%?\\t%1, %2"
+ [(set_attr "predicable" "yes")])
+
+;;
+;; [sqshl_si]
+;;
+(define_insn "mve_sqshl_si"
+ [(set (match_operand:SI 0 "arm_general_register_operand" "+r")
+ (ss_ashift:SI (match_operand:DI 1 "arm_general_register_operand" "r")
+ (match_operand:SI 2 "arm_reg_or_long_shift_imm" "rPg")))]
+ "TARGET_HAVE_MVE"
+ "sqshl%?\\t%1, %2"
+ [(set_attr "predicable" "yes")])
+
+;;
+;; [srshr_si]
+;;
+(define_insn "mve_srshr_si"
+ [(set (match_operand:SI 0 "arm_general_register_operand" "+r")
+ (unspec:SI [(match_operand:DI 1 "arm_general_register_operand" "r")
+ (match_operand:SI 2 "arm_reg_or_long_shift_imm" "rPg")]
+ SRSHR))]
+ "TARGET_HAVE_MVE"
+ "srshr%?\\t%1, %2"
+ [(set_attr "predicable" "yes")])
+
+;;
+;; [srshrl_di]
+;;
+(define_insn "mve_srshrl_di"
+ [(set (match_operand:DI 0 "arm_general_register_operand" "+r")
+ (unspec:DI [(match_operand:DI 1 "arm_general_register_operand" "r")
+ (match_operand:SI 2 "arm_reg_or_long_shift_imm" "rPg")]
+ SRSHRL))]
+ "TARGET_HAVE_MVE"
+ "srshrl%?\\t%Q1, %R1, %2"
+ [(set_attr "predicable" "yes")])
+
+;;
+;; [sqshll_di]
+;;
+(define_insn "mve_sqshll_di"
+ [(set (match_operand:DI 0 "arm_general_register_operand" "+r")
+ (ss_ashift:DI (match_operand:DI 1 "arm_general_register_operand" "r")
+ (match_operand:SI 2 "arm_reg_or_long_shift_imm" "rPg")))]
+ "TARGET_HAVE_MVE"
+ "sqshll%?\\t%Q1, %R1, %2"
+ [(set_attr "predicable" "yes")])
new file mode 100644
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */
+/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */
+
+#include "arm_mve.h"
+
+int64_t
+asrl_reg (int64_t longval3, int32_t x)
+{
+ return asrl (longval3, x);
+}
+
+/* { dg-final { scan-assembler "asrl\\tr\[0-9\]+, r\[0-9\]+, r\[0-9\]+" } } */
new file mode 100644
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */
+/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */
+
+#include "arm_mve.h"
+
+uint64_t
+lsll_reg (uint64_t longval3, int32_t x)
+{
+ return lsll (longval3, x);
+}
+
+/* { dg-final { scan-assembler "lsll\\tr\[0-9\]+, r\[0-9\]+, r\[0-9\]+" } } */
new file mode 100644
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */
+/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */
+
+#include "arm_mve.h"
+
+int32_t
+sqrshr_reg (int32_t longval3, int32_t x)
+{
+ return sqrshr (longval3, x);
+}
+
+/* { dg-final { scan-assembler "sqrshr\\tr\[0-9\]+, r\[0-9\]+" } } */
new file mode 100644
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */
+/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */
+
+#include "arm_mve.h"
+
+int64_t
+sqrshrl_reg (int64_t longval3, int32_t x)
+{
+ return sqrshrl_sat48 (longval3, x);
+}
+
+/* { dg-final { scan-assembler "sqrshrl\\tr\[0-9\]+, r\[0-9\]+, #48, r\[0-9\]+" } } */
new file mode 100644
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */
+/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */
+
+#include "arm_mve.h"
+
+int64_t
+sqrshrl_reg (int64_t longval3, int32_t x)
+{
+ return sqrshrl (longval3, x);
+}
+
+/* { dg-final { scan-assembler "sqrshrl\\tr\[0-9\]+, r\[0-9\]+, #64, r\[0-9\]+" } } */
new file mode 100644
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */
+/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */
+
+#include "arm_mve.h"
+
+int32_t
+sqshl_imm (int32_t longval3)
+{
+ return sqshl (longval3, 25);
+}
+
+/* { dg-final { scan-assembler "sqshl\\tr\[0-9\]+, #25" } } */
new file mode 100644
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */
+/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */
+
+#include "arm_mve.h"
+
+int64_t
+sqshll_imm(int64_t value)
+{
+ return sqshll (value, 21);
+}
+
+/* { dg-final { scan-assembler "sqshll\\tr\[0-9\]+, r\[0-9\]+, #21" } } */
new file mode 100644
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */
+/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */
+
+#include "arm_mve.h"
+
+int32_t
+srshr_imm (int32_t longval3)
+{
+ return srshr (longval3, 25);
+}
+
+/* { dg-final { scan-assembler "srshr\\tr\[0-9\]+, #25" } } */
new file mode 100644
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */
+/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */
+
+#include "arm_mve.h"
+
+int64_t
+srshrl_imm(int64_t value)
+{
+ return srshrl (value, 21);
+}
+
+/* { dg-final { scan-assembler "srshrl\\tr\[0-9\]+, r\[0-9\]+, #21" } } */
new file mode 100644
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */
+/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */
+
+#include "arm_mve.h"
+
+uint32_t
+uqrshl_reg (uint32_t longval3, int32_t x)
+{
+ return uqrshl (longval3, x);
+}
+
+/* { dg-final { scan-assembler "uqrshl\\tr\[0-9\]+, r\[0-9\]+" } } */
new file mode 100644
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */
+/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */
+
+#include "arm_mve.h"
+
+uint64_t
+uqrshll_reg (uint64_t longval3, int32_t x)
+{
+ return uqrshll_sat48 (longval3, x);
+}
+
+/* { dg-final { scan-assembler "uqrshll\\tr\[0-9\]+, r\[0-9\]+, #48, r\[0-9\]+" } } */
new file mode 100644
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */
+/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */
+
+#include "arm_mve.h"
+
+uint64_t
+uqrshll_reg (uint64_t longval3, int32_t x)
+{
+ return uqrshll (longval3, x);
+}
+
+/* { dg-final { scan-assembler "uqrshll\\tr\[0-9\]+, r\[0-9\]+, #64, r\[0-9\]+" } } */
new file mode 100644
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */
+/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */
+
+#include "arm_mve.h"
+
+uint32_t
+uqshl_imm (uint32_t longval3)
+{
+ return uqshl (longval3, 21);
+}
+
+/* { dg-final { scan-assembler "uqshl\\tr\[0-9\]+, #21" } } */
new file mode 100644
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */
+/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */
+
+#include "arm_mve.h"
+
+uint64_t
+uqshll_imm(uint64_t value)
+{
+ return uqshll (value, 21);
+}
+
+/* { dg-final { scan-assembler "uqshll\\tr\[0-9\]+, r\[0-9\]+, #21" } } */
new file mode 100644
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */
+/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */
+
+#include "arm_mve.h"
+
+uint64_t
+urshr_imm (uint32_t longval3)
+{
+ return urshr (longval3, 21);
+}
+
+/* { dg-final { scan-assembler "urshr\\tr\[0-9\]+, #21" } } */
new file mode 100644
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */
+/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */
+
+#include "arm_mve.h"
+
+uint64_t
+urshrl_imm(uint64_t value)
+{
+ return urshrl (value, 21);
+}
+
+/* { dg-final { scan-assembler "urshrl\\tr\[0-9\]+, r\[0-9\]+, #21" } } */
Hello, This patch supports following MVE ACLE scalar shift intrinsics. sqrshr, sqrshrl, sqrshrl_sat48, sqshl, sqshll, srshr, srshrl, uqrshl, uqrshll, uqrshll_sat48, uqshl, uqshll, urshr, urshrl, lsll, asrl. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics Regression tested on arm-none-eabi and found no regressions. Ok for trunk? Thanks, Srinath. gcc/ChangeLog: 2019-11-08 Srinath Parvathaneni <srinath.parvathaneni@arm.com> * config/arm/arm-builtins.c (LSLL_QUALIFIERS): Define builtin qualifier. (UQSHL_QUALIFIERS): Likewise. (ASRL_QUALIFIERS): Likewise. (SQSHL_QUALIFIERS): Likewise. * config/arm/arm_mve.h (sqrshr): Define macro. (sqrshrl): Likewise. (sqrshrl_sat48): Likewise. (sqshl): Likewise. (sqshll): Likewise. (srshr): Likewise. (srshrl): Likewise. (uqrshl): Likewise. (uqrshll): Likewise. (uqrshll_sat48): Likewise. (uqshl): Likewise. (uqshll): Likewise. (urshr): Likewise. (urshrl): Likewise. (lsll): Likewise. (asrl): Likewise. (__arm_lsll): Define intrinsic. (__arm_asrl): Likewise. (__arm_uqrshll): Likewise. (__arm_uqrshll_sat48): Likewise. (__arm_sqrshrl): Likewise. (__arm_sqrshrl_sat48): Likewise. (__arm_uqshll): Likewise. (__arm_urshrl): Likewise. (__arm_srshrl): Likewise. (__arm_sqshll): Likewise. (__arm_uqrshl): Likewise. (__arm_sqrshr): Likewise. (__arm_uqshl): Likewise. (__arm_urshr): Likewise. (__arm_sqshl): Likewise. (__arm_srshr): Likewise. * config/arm/arm_mve_builtins.def (LSLL_QUALIFIERS): Use builtin qualifier. (UQSHL_QUALIFIERS): Likewise. (ASRL_QUALIFIERS): Likewise. (SQSHL_QUALIFIERS): Likewise. * config/arm/mve.md (mve_uqrshll_sat<supf>_di): Define RTL pattern. (mve_sqrshrl_sat<supf>_di): Likewise (mve_uqrshl_si): Likewise (mve_sqrshr_si): Likewise (mve_uqshll_di): Likewise (mve_urshrl_di): Likewise (mve_uqshl_si): Likewise (mve_urshr_si): Likewise (mve_sqshl_si): Likewise (mve_srshr_si): Likewise (mve_srshrl_di): Likewise (mve_sqshll_di): Likewise gcc/testsuite/ChangeLog: 2019-11-08 Srinath Parvathaneni <srinath.parvathaneni@arm.com> * gcc.target/arm/mve/intrinsics/asrl.c: New test. * gcc.target/arm/mve/intrinsics/lsll.c: Likewise. * gcc.target/arm/mve/intrinsics/sqrshr.c: Likewise. * gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c: Likewise. * gcc.target/arm/mve/intrinsics/sqrshrl_sat64.c: Likewise. * gcc.target/arm/mve/intrinsics/sqshl.c: Likewise. * gcc.target/arm/mve/intrinsics/sqshll.c: Likewise. * gcc.target/arm/mve/intrinsics/srshr.c: Likewise. * gcc.target/arm/mve/intrinsics/srshrl.c: Likewise. * gcc.target/arm/mve/intrinsics/uqrshl.c: Likewise. * gcc.target/arm/mve/intrinsics/uqrshll_sat48.c: Likewise. * gcc.target/arm/mve/intrinsics/uqrshll_sat64.c: Likewise. * gcc.target/arm/mve/intrinsics/uqshl.c: Likewise. * gcc.target/arm/mve/intrinsics/uqshll.c: Likewise. * gcc.target/arm/mve/intrinsics/urshr.c: Likewise. * gcc.target/arm/mve/intrinsics/urshrl.c: Likewise. ############### Attachment also inlined for ease of reply ############### diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index 9e87dff264d6b535f64407f669c6e83b0ed639a6..31bff8511e368f8e789297818e9b0b9f885463ae 100644 --- a/gcc/config/arm/arm-builtins.c +++ b/gcc/config/arm/arm-builtins.c @@ -738,6 +738,26 @@ arm_strsbwbu_p_qualifiers[SIMD_MAX_BUILTIN_ARGS] qualifier_unsigned, qualifier_unsigned}; #define STRSBWBU_P_QUALIFIERS (arm_strsbwbu_p_qualifiers) +static enum arm_type_qualifiers +arm_lsll_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_unsigned, qualifier_unsigned, qualifier_none}; +#define LSLL_QUALIFIERS (arm_lsll_qualifiers) + +static enum arm_type_qualifiers +arm_uqshl_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_unsigned, qualifier_unsigned, qualifier_const}; +#define UQSHL_QUALIFIERS (arm_uqshl_qualifiers) + +static enum arm_type_qualifiers +arm_asrl_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_none, qualifier_none, qualifier_none}; +#define ASRL_QUALIFIERS (arm_asrl_qualifiers) + +static enum arm_type_qualifiers +arm_sqshl_qualifiers[SIMD_MAX_BUILTIN_ARGS] + = { qualifier_unsigned, qualifier_unsigned, qualifier_const}; +#define SQSHL_QUALIFIERS (arm_sqshl_qualifiers) + /* End of Qualifier for MVE builtins. */ /* void ([T element type] *, T, immediate). */ diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 9dcf8d692670cd8552fade9868bc051683553b91..2adae7f8b21f44aa3b80231b89bd68bcd0812611 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -2526,6 +2526,22 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t; #define vgetq_lane_u16(__a, __idx) __arm_vgetq_lane_u16(__a, __idx) #define vgetq_lane_u32(__a, __idx) __arm_vgetq_lane_u32(__a, __idx) #define vgetq_lane_u64(__a, __idx) __arm_vgetq_lane_u64(__a, __idx) +#define sqrshr(__p0, __p1) __arm_sqrshr(__p0, __p1) +#define sqrshrl(__p0, __p1) __arm_sqrshrl(__p0, __p1) +#define sqrshrl_sat48(__p0, __p1) __arm_sqrshrl_sat48(__p0, __p1) +#define sqshl(__p0, __p1) __arm_sqshl(__p0, __p1) +#define sqshll(__p0, __p1) __arm_sqshll(__p0, __p1) +#define srshr(__p0, __p1) __arm_srshr(__p0, __p1) +#define srshrl(__p0, __p1) __arm_srshrl(__p0, __p1) +#define uqrshl(__p0, __p1) __arm_uqrshl(__p0, __p1) +#define uqrshll(__p0, __p1) __arm_uqrshll(__p0, __p1) +#define uqrshll_sat48(__p0, __p1) __arm_uqrshll_sat48(__p0, __p1) +#define uqshl(__p0, __p1) __arm_uqshl(__p0, __p1) +#define uqshll(__p0, __p1) __arm_uqshll(__p0, __p1) +#define urshr(__p0, __p1) __arm_urshr(__p0, __p1) +#define urshrl(__p0, __p1) __arm_urshrl(__p0, __p1) +#define lsll(__p0, __p1) __arm_lsll(__p0, __p1) +#define asrl(__p0, __p1) __arm_asrl(__p0, __p1) #endif /* For big-endian, GCC's vector indices are reversed within each 64 bits @@ -16539,6 +16555,118 @@ __arm_vgetq_lane_u64 (uint64x2_t __a, const int __idx) return __a[__ARM_LANEQ(__a,__idx)]; } +__extension__ extern __inline uint64_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_lsll (uint64_t value, int32_t shift) +{ + return (value << shift); +} + +__extension__ extern __inline int64_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_asrl (int64_t value, int32_t shift) +{ + return (value >> shift); +} + +__extension__ extern __inline uint64_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_uqrshll (uint64_t value, int32_t shift) +{ + return __builtin_mve_uqrshll_sat64_di (value, shift); +} + +__extension__ extern __inline uint64_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_uqrshll_sat48 (uint64_t value, int32_t shift) +{ + return __builtin_mve_uqrshll_sat48_di (value, shift); +} + +__extension__ extern __inline int64_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_sqrshrl (int64_t value, int32_t shift) +{ + return __builtin_mve_sqrshrl_sat64_di (value, shift); +} + +__extension__ extern __inline int64_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_sqrshrl_sat48 (int64_t value, int32_t shift) +{ + return __builtin_mve_sqrshrl_sat48_di (value, shift); +} + +__extension__ extern __inline uint64_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_uqshll (uint64_t value, const int shift) +{ + return __builtin_mve_uqshll_di (value, shift); +} + +__extension__ extern __inline uint64_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_urshrl (uint64_t value, const int shift) +{ + return __builtin_mve_urshrl_di (value, shift); +} + +__extension__ extern __inline int64_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_srshrl (int64_t value, const int shift) +{ + return __builtin_mve_srshrl_di (value, shift); +} + +__extension__ extern __inline int64_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_sqshll (int64_t value, const int shift) +{ + return __builtin_mve_sqshll_di (value, shift); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_uqrshl (uint32_t value, int32_t shift) +{ + return __builtin_mve_uqrshl_si (value, shift); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_sqrshr (int32_t value, int32_t shift) +{ + return __builtin_mve_sqrshr_si (value, shift); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_uqshl (uint32_t value, const int shift) +{ + return __builtin_mve_uqshl_si (value, shift); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_urshr (uint32_t value, const int shift) +{ + return __builtin_mve_urshr_si (value, shift); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_sqshl (int32_t value, const int shift) +{ + return __builtin_mve_sqshl_si (value, shift); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_srshr (int32_t value, const int shift) +{ + return __builtin_mve_srshr_si (value, shift); +} + #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ __extension__ extern __inline void diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def index 638dcbc819034bf2c8428ff40f0e4d811763d80e..c23fe88ad05f8ee6c03127066fdf5afa593df944 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -876,3 +876,17 @@ VAR1 (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE, vsbcq_m_u, v4si) VAR5 (STORE1, vst2q, v16qi, v8hi, v4si, v8hf, v4sf) VAR5 (LOAD1, vld4q, v16qi, v8hi, v4si, v8hf, v4sf) VAR5 (LOAD1, vld2q, v16qi, v8hi, v4si, v8hf, v4sf) +VAR1 (ASRL, sqrshr_,si) +VAR1 (ASRL, sqrshrl_sat64_,di) +VAR1 (ASRL, sqrshrl_sat48_,di) +VAR1 (LSLL, uqrshl_, si) +VAR1 (LSLL, uqrshll_sat64_, di) +VAR1 (LSLL, uqrshll_sat48_, di) +VAR1 (SQSHL,srshr_,si) +VAR1 (SQSHL,srshrl_,di) +VAR1 (SQSHL,sqshl_,si) +VAR1 (SQSHL,sqshll_,di) +VAR1 (UQSHL, urshr_, si) +VAR1 (UQSHL, urshrl_, di) +VAR1 (UQSHL, uqshl_, si) +VAR1 (UQSHL, uqshll_, di) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index b679511e42ce909cc9ef19e1cb790e8a5254d538..bbd54ad71d0b85fd4711007dd93af7a2788b2cf4 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -214,7 +214,9 @@ VLDRDQGBWB_S VLDRDQGBWB_U VADCQ_U VADCQ_M_U VADCQ_S VADCQ_M_S VSBCIQ_U VSBCIQ_S VSBCIQ_M_U VSBCIQ_M_S VSBCQ_U VSBCQ_S VSBCQ_M_U VSBCQ_M_S VADCIQ_U VADCIQ_M_U - VADCIQ_S VADCIQ_M_S VLD2Q VLD4Q VST2Q]) + VADCIQ_S VADCIQ_M_S VLD2Q VLD4Q VST2Q SRSHRL SRSHR + URSHR URSHRL SQRSHR UQRSHL UQRSHLL_64 + UQRSHLL_48 SQRSHRL_64 SQRSHRL_48]) (define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI") (V4SF "V4SI")]) @@ -391,7 +393,8 @@ (VSBCIQ_M_U "u") (VSBCIQ_S "s") (VSBCIQ_M_S "s") (VADCQ_U "u") (VADCQ_M_U "u") (VADCQ_S "s") (VADCIQ_U "u") (VADCIQ_M_U "u") (VADCIQ_S "s") - (VADCIQ_M_S "s")]) + (VADCIQ_M_S "s") (SQRSHRL_64 "64") (SQRSHRL_48 "48") + (UQRSHLL_64 "64") (UQRSHLL_48 "48")]) (define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32") (VCTP64Q "64") (VCTP8Q_M "8") (VCTP16Q_M "16") @@ -654,7 +657,8 @@ (define_int_iterator VSBCIQ_M [VSBCIQ_M_U VSBCIQ_M_S]) (define_int_iterator VADCQ [VADCQ_U VADCQ_S]) (define_int_iterator VADCQ_M [VADCQ_M_U VADCQ_M_S]) - +(define_int_iterator UQRSHLLQ [UQRSHLL_64 UQRSHLL_48]) +(define_int_iterator SQRSHRLQ [SQRSHRL_64 SQRSHRL_48]) (define_insn "*mve_mov<mode>" [(set (match_operand:MVE_types 0 "s_register_operand" "=w,w,r,w,w,r,w") @@ -10983,3 +10987,143 @@ return "vmov\t%f0, %J1, %K1"; } [(set_attr "type" "mve_move")]) + +;; +;; [uqrshll_di] +;; +(define_insn "mve_uqrshll_sat<supf>_di" + [(set (match_operand:DI 0 "arm_general_register_operand" "+r") + (unspec:DI [(match_operand:DI 1 "arm_general_register_operand" "r") + (match_operand:SI 2 "s_register_operand" "r")] + UQRSHLLQ))] + "TARGET_HAVE_MVE" + "uqrshll%?\\t%Q1, %R1, #<supf>, %2" + [(set_attr "predicable" "yes")]) + +;; +;; [sqrshrl_di] +;; +(define_insn "mve_sqrshrl_sat<supf>_di" + [(set (match_operand:DI 0 "arm_general_register_operand" "+r") + (unspec:DI [(match_operand:DI 1 "arm_general_register_operand" "r") + (match_operand:SI 2 "s_register_operand" "r")] + SQRSHRLQ))] + "TARGET_HAVE_MVE" + "sqrshrl%?\\t%Q1, %R1, #<supf>, %2" + [(set_attr "predicable" "yes")]) + +;; +;; [uqrshl_si] +;; +(define_insn "mve_uqrshl_si" + [(set (match_operand:SI 0 "arm_general_register_operand" "+r") + (unspec:SI [(match_operand:SI 1 "arm_general_register_operand" "r") + (match_operand:SI 2 "s_register_operand" "r")] + UQRSHL))] + "TARGET_HAVE_MVE" + "uqrshl%?\\t%1, %2" + [(set_attr "predicable" "yes")]) + +;; +;; [sqrshr_si] +;; +(define_insn "mve_sqrshr_si" + [(set (match_operand:SI 0 "arm_general_register_operand" "+r") + (unspec:SI [(match_operand:SI 1 "arm_general_register_operand" "r") + (match_operand:SI 2 "s_register_operand" "r")] + SQRSHR))] + "TARGET_HAVE_MVE" + "sqrshr%?\\t%1, %2" + [(set_attr "predicable" "yes")]) + +;; +;; [uqshll_di] +;; +(define_insn "mve_uqshll_di" + [(set (match_operand:DI 0 "arm_general_register_operand" "+r") + (us_ashift:DI (match_operand:DI 1 "arm_general_register_operand" "r") + (match_operand:SI 2 "arm_reg_or_long_shift_imm" "rPg")))] + "TARGET_HAVE_MVE" + "uqshll%?\\t%Q1, %R1, %2" + [(set_attr "predicable" "yes")]) + +;; +;; [urshrl_di] +;; +(define_insn "mve_urshrl_di" + [(set (match_operand:DI 0 "arm_general_register_operand" "+r") + (unspec:DI [(match_operand:DI 1 "arm_general_register_operand" "r") + (match_operand:SI 2 "arm_reg_or_long_shift_imm" "rPg")] + URSHRL))] + "TARGET_HAVE_MVE" + "urshrl%?\\t%Q1, %R1, %2" + [(set_attr "predicable" "yes")]) + +;; +;; [uqshl_si] +;; +(define_insn "mve_uqshl_si" + [(set (match_operand:SI 0 "arm_general_register_operand" "+r") + (us_ashift:SI (match_operand:SI 1 "arm_general_register_operand" "r") + (match_operand:SI 2 "arm_reg_or_long_shift_imm" "rPg")))] + "TARGET_HAVE_MVE" + "uqshl%?\\t%1, %2" + [(set_attr "predicable" "yes")]) + +;; +;; [urshr_si] +;; +(define_insn "mve_urshr_si" + [(set (match_operand:SI 0 "arm_general_register_operand" "+r") + (unspec:SI [(match_operand:SI 1 "arm_general_register_operand" "r") + (match_operand:SI 2 "arm_reg_or_long_shift_imm" "rPg")] + URSHR))] + "TARGET_HAVE_MVE" + "urshr%?\\t%1, %2" + [(set_attr "predicable" "yes")]) + +;; +;; [sqshl_si] +;; +(define_insn "mve_sqshl_si" + [(set (match_operand:SI 0 "arm_general_register_operand" "+r") + (ss_ashift:SI (match_operand:DI 1 "arm_general_register_operand" "r") + (match_operand:SI 2 "arm_reg_or_long_shift_imm" "rPg")))] + "TARGET_HAVE_MVE" + "sqshl%?\\t%1, %2" + [(set_attr "predicable" "yes")]) + +;; +;; [srshr_si] +;; +(define_insn "mve_srshr_si" + [(set (match_operand:SI 0 "arm_general_register_operand" "+r") + (unspec:SI [(match_operand:DI 1 "arm_general_register_operand" "r") + (match_operand:SI 2 "arm_reg_or_long_shift_imm" "rPg")] + SRSHR))] + "TARGET_HAVE_MVE" + "srshr%?\\t%1, %2" + [(set_attr "predicable" "yes")]) + +;; +;; [srshrl_di] +;; +(define_insn "mve_srshrl_di" + [(set (match_operand:DI 0 "arm_general_register_operand" "+r") + (unspec:DI [(match_operand:DI 1 "arm_general_register_operand" "r") + (match_operand:SI 2 "arm_reg_or_long_shift_imm" "rPg")] + SRSHRL))] + "TARGET_HAVE_MVE" + "srshrl%?\\t%Q1, %R1, %2" + [(set_attr "predicable" "yes")]) + +;; +;; [sqshll_di] +;; +(define_insn "mve_sqshll_di" + [(set (match_operand:DI 0 "arm_general_register_operand" "+r") + (ss_ashift:DI (match_operand:DI 1 "arm_general_register_operand" "r") + (match_operand:SI 2 "arm_reg_or_long_shift_imm" "rPg")))] + "TARGET_HAVE_MVE" + "sqshll%?\\t%Q1, %R1, %2" + [(set_attr "predicable" "yes")]) diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/asrl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/asrl.c new file mode 100644 index 0000000000000000000000000000000000000000..ead9c51003f1a309fe2afb619a582bd42ee61ecb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/asrl.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +int64_t +asrl_reg (int64_t longval3, int32_t x) +{ + return asrl (longval3, x); +} + +/* { dg-final { scan-assembler "asrl\\tr\[0-9\]+, r\[0-9\]+, r\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/lsll.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/lsll.c new file mode 100644 index 0000000000000000000000000000000000000000..fac4a41f4f779e15f50b84f29e0c87558a27d30c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/lsll.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +uint64_t +lsll_reg (uint64_t longval3, int32_t x) +{ + return lsll (longval3, x); +} + +/* { dg-final { scan-assembler "lsll\\tr\[0-9\]+, r\[0-9\]+, r\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshr.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshr.c new file mode 100644 index 0000000000000000000000000000000000000000..def379d59c9ad99add67ea5976eb285588a49f18 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshr.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +int32_t +sqrshr_reg (int32_t longval3, int32_t x) +{ + return sqrshr (longval3, x); +} + +/* { dg-final { scan-assembler "sqrshr\\tr\[0-9\]+, r\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c new file mode 100644 index 0000000000000000000000000000000000000000..0a8606747c45aec190dbde705b5909dc2c4a1205 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +int64_t +sqrshrl_reg (int64_t longval3, int32_t x) +{ + return sqrshrl_sat48 (longval3, x); +} + +/* { dg-final { scan-assembler "sqrshrl\\tr\[0-9\]+, r\[0-9\]+, #48, r\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshrl_sat64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshrl_sat64.c new file mode 100644 index 0000000000000000000000000000000000000000..32d52496343311ac1ec6036cbef81c9c6266d4a5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshrl_sat64.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +int64_t +sqrshrl_reg (int64_t longval3, int32_t x) +{ + return sqrshrl (longval3, x); +} + +/* { dg-final { scan-assembler "sqrshrl\\tr\[0-9\]+, r\[0-9\]+, #64, r\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshl.c new file mode 100644 index 0000000000000000000000000000000000000000..a546ff51681e5615f7961db3f1ee59b526cd7688 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshl.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +int32_t +sqshl_imm (int32_t longval3) +{ + return sqshl (longval3, 25); +} + +/* { dg-final { scan-assembler "sqshl\\tr\[0-9\]+, #25" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshll.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshll.c new file mode 100644 index 0000000000000000000000000000000000000000..8784b70155ae6193be8a9700dd6a0b4a34bf233b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshll.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +int64_t +sqshll_imm(int64_t value) +{ + return sqshll (value, 21); +} + +/* { dg-final { scan-assembler "sqshll\\tr\[0-9\]+, r\[0-9\]+, #21" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c new file mode 100644 index 0000000000000000000000000000000000000000..d48d65a1f05a3ea679129bac92ea8cf55f44bff5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +int32_t +srshr_imm (int32_t longval3) +{ + return srshr (longval3, 25); +} + +/* { dg-final { scan-assembler "srshr\\tr\[0-9\]+, #25" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c new file mode 100644 index 0000000000000000000000000000000000000000..260285b28865337eb7e589a25a00898f8b636956 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +int64_t +srshrl_imm(int64_t value) +{ + return srshrl (value, 21); +} + +/* { dg-final { scan-assembler "srshrl\\tr\[0-9\]+, r\[0-9\]+, #21" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshl.c new file mode 100644 index 0000000000000000000000000000000000000000..e23e644ec948a7af3341c0743569a1db8572e652 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshl.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +uint32_t +uqrshl_reg (uint32_t longval3, int32_t x) +{ + return uqrshl (longval3, x); +} + +/* { dg-final { scan-assembler "uqrshl\\tr\[0-9\]+, r\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshll_sat48.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshll_sat48.c new file mode 100644 index 0000000000000000000000000000000000000000..ed7a550b92bff6097d831654e7601a6d8aee6153 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshll_sat48.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +uint64_t +uqrshll_reg (uint64_t longval3, int32_t x) +{ + return uqrshll_sat48 (longval3, x); +} + +/* { dg-final { scan-assembler "uqrshll\\tr\[0-9\]+, r\[0-9\]+, #48, r\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshll_sat64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshll_sat64.c new file mode 100644 index 0000000000000000000000000000000000000000..1d75ea1f878db12e8b5e92c886c7524ceebb0284 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshll_sat64.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +uint64_t +uqrshll_reg (uint64_t longval3, int32_t x) +{ + return uqrshll (longval3, x); +} + +/* { dg-final { scan-assembler "uqrshll\\tr\[0-9\]+, r\[0-9\]+, #64, r\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c new file mode 100644 index 0000000000000000000000000000000000000000..92e8748e5ec5d3426523b89c57e6b698aa4b351c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +uint32_t +uqshl_imm (uint32_t longval3) +{ + return uqshl (longval3, 21); +} + +/* { dg-final { scan-assembler "uqshl\\tr\[0-9\]+, #21" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c new file mode 100644 index 0000000000000000000000000000000000000000..e4416e15144cc8939e5c57773049d85293073c07 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +uint64_t +uqshll_imm(uint64_t value) +{ + return uqshll (value, 21); +} + +/* { dg-final { scan-assembler "uqshll\\tr\[0-9\]+, r\[0-9\]+, #21" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c new file mode 100644 index 0000000000000000000000000000000000000000..1526270e778a7757e4fcfeec7d45b738806adbc8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +uint64_t +urshr_imm (uint32_t longval3) +{ + return urshr (longval3, 21); +} + +/* { dg-final { scan-assembler "urshr\\tr\[0-9\]+, #21" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c new file mode 100644 index 0000000000000000000000000000000000000000..032e6e31670c19ab2f14915dc0af0a63459dd156 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+mve -mfloat-abi=hard -O2" } */ +/* { dg-skip-if "Skip if not auto" {*-*-*} {"-mfpu=*"} {"-mfpu=auto"} } */ + +#include "arm_mve.h" + +uint64_t +urshrl_imm(uint64_t value) +{ + return urshrl (value, 21); +} + +/* { dg-final { scan-assembler "urshrl\\tr\[0-9\]+, r\[0-9\]+, #21" } } */