From patchwork Tue Jan 16 16:32:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wilco Dijkstra X-Patchwork-Id: 861752 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-471390-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="L1nwjfY0"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zLbP14G3Cz9ryk for ; Wed, 17 Jan 2018 03:32:52 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:content-type :content-transfer-encoding:mime-version; q=dns; s=default; b=Og+ Z88VnUIi5WTA5GJmpxJEj2ONlotWqQo3OobTmAAqAKlvikwvC7SKAQdBDRbu30kK r9/t2Ulq3dRolREj8ulidLwbuWyA3X6ot1JOPhvtj9V6CHo71jKbJZ318+TjCV1m 0GA8KA1Mocpc7h3XNM9z4HJ4V2sQLMqr+KM2r8DM= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:content-type :content-transfer-encoding:mime-version; s=default; bh=tz/lplw6i veGLwKZXGXwK0+Gr98=; b=L1nwjfY0k2O1z+TA/kFtslAQHqr06/RgwXClCAQ/A lXXKXlEFR1wtSlSD6f7Mjt7rjAqj0sWyjvLN86xNb6eATqND+6wcTBiG54SuIZny PwphIiAY1m86jm5/ifa+1Q3Mn2gty4AQNxicJpWkRt/cPvkEi1S+GEKiSM831+wo X0= Received: (qmail 22254 invoked by alias); 16 Jan 2018 16:32:44 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 22243 invoked by uid 89); 16 Jan 2018 16:32:43 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.2 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_HELO_PASS, SPF_PASS autolearn=ham version=3.3.2 spammy=wr, ww, 13179, lax X-HELO: EUR02-HE1-obe.outbound.protection.outlook.com Received: from mail-eopbgr10067.outbound.protection.outlook.com (HELO EUR02-HE1-obe.outbound.protection.outlook.com) (40.107.1.67) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 16 Jan 2018 16:32:40 +0000 Received: from DB6PR0801MB2053.eurprd08.prod.outlook.com (10.168.86.22) by VI1PR08MB2671.eurprd08.prod.outlook.com (10.175.245.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.407.7; Tue, 16 Jan 2018 16:32:36 +0000 Received: from DB6PR0801MB2053.eurprd08.prod.outlook.com ([fe80::3cba:f6a6:c08c:8f0e]) by DB6PR0801MB2053.eurprd08.prod.outlook.com ([fe80::3cba:f6a6:c08c:8f0e%18]) with mapi id 15.20.0407.012; Tue, 16 Jan 2018 16:32:36 +0000 From: Wilco Dijkstra To: GCC Patches CC: nd , James Greenhalgh Subject: [PATCH v2][AArch64] Remove remaining uses of * in patterns Date: Tue, 16 Jan 2018 16:32:36 +0000 Message-ID: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Wilco.Dijkstra@arm.com; x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; VI1PR08MB2671; 6:XskGA0hcsaj4Z6+spHh7Dmbjo6MqWUjksx3gE8PIFuabVAf6dAKW+4WVCete1QFlAF/YVsLWt7uomYSOFocYmISq7bcWBfkA5WOBAlc7JCTr2CW2ZCEhr6nkAY3iYvYzFmONfgWIstCeiUJmij9IUad2ON/R09sVkBhNf5ZN8Q/kf9KV7Ga+bWWkJbEesiiG27HMSW0we4EOyavbey4IKKhCSNEpRdvkav37VXIdxi3oAy5IVegALkWK0m6NlhiINahNfTARjN8iLmAlZ2Bu5WrG/sBS7OS2XfTMOWc1mFMCZTzVjJCmpPvL61IUu8Vx87wApkuaB2uiVggxgzWlpgEyhvc1isXNgTkVFp1wcMBVsKLqUFvaWe1/hvcBVdXY; 5:GyfWZwCt4nJ17MfX0R/3DcfuxLlLXZJeHsMjO2n/4OL6lsVozgsKA6zQHgbTnoIRxH2CQlKJeQi7/jBzkzRERrR+Ro7sI4NucbGJ+ZOMHXGwvAOPk2XPtMGx4ZAuUyMJZhJedH8ho53RECmi6qIDer0bHCk2ODxkwXye65Jy/4Q=; 24:HDt8cRMxjTReLxRQMszbEwwdBAToWt7NZuD0FlaWoF0D/pLH1DYz82TAP004TPTh6zaApsz0ngis5sVB/SgHHgjHqZVwqG7ffcuzFC8WdtU=; 7:zU8+pYi3xWD62WkOMXVcgcMgBPtXto+A7We0TLfoHOLeutx23JzZcHFUp/ChlD3TFQIhKx2rR2Ux1xecuMi13efUdym7LmeBkN4442PjF0POlnpUh/5KmhoaV6f9IoWsEbAtwVYDVWhY2/75wD6AR1j7zccp4W8kcoM75AoMYm5R64sMfuOllVK8AsHPrIJQBJ2FIxitsi8bS4OEoVUfbGHvn0qWGnVr12RLt3nOSjee6bicAvHMWZ395Uayh/q9 x-ms-exchange-antispam-srfa-diagnostics: SSOS;SSOR; x-ms-office365-filtering-ht: Tenant x-ms-office365-filtering-correlation-id: 6677a3b4-7c9b-4c6c-ed19-08d55cfec061 x-microsoft-antispam: UriScan:; BCL:0; PCL:0; RULEID:(7020095)(4652020)(48565401081)(5600026)(4604075)(3008032)(2017052603307)(7153060)(7193020); SRVR:VI1PR08MB2671; x-ms-traffictypediagnostic: VI1PR08MB2671: nodisclaimer: True x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(180628864354917); x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(6040470)(2401047)(5005006)(8121501046)(93006095)(93001095)(3231023)(944501161)(10201501046)(3002001)(6055026)(6041268)(20161123562045)(20161123564045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123560045)(20161123558120)(6072148)(201708071742011); SRVR:VI1PR08MB2671; BCL:0; PCL:0; RULEID:(100000803101)(100110400095); SRVR:VI1PR08MB2671; x-forefront-prvs: 0554B1F54F x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(396003)(39380400002)(366004)(376002)(346002)(39860400002)(54534003)(189003)(199004)(377424004)(55016002)(25786009)(68736007)(105586002)(5250100002)(53936002)(97736004)(4326008)(2900100001)(81156014)(14454004)(7736002)(81166006)(8676002)(305945005)(8936002)(3280700002)(6436002)(2906002)(3660700001)(74316002)(26005)(9686003)(66066001)(6916009)(99286004)(33656002)(54906003)(72206003)(3846002)(6116002)(5660300001)(7696005)(59450400001)(6506007)(102836004)(478600001)(575784001)(86362001)(106356001)(316002); DIR:OUT; SFP:1101; SCL:1; SRVR:VI1PR08MB2671; H:DB6PR0801MB2053.eurprd08.prod.outlook.com; FPR:; SPF:None; PTR:InfoNoRecords; MX:1; A:1; LANG:en; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: xuxvOX1ITfBJM8ZLeNN31OjFpue13BuyngciTSULXXZzsyEUuRbOPSn4BhdRnKN4uZLU8e6I7+/Pq17Qjj1nGw== spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6677a3b4-7c9b-4c6c-ed19-08d55cfec061 X-MS-Exchange-CrossTenant-originalarrivaltime: 16 Jan 2018 16:32:36.1103 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR08MB2671 v2: Rebased after the big SVE commits Remove the remaining uses of '*' from aarch64.md. Using '*' in alternatives is typically incorrect as it tells the register allocator to ignore those alternatives. Also add a missing '?' so we prefer a floating point register for same-size int<->fp conversions. Passes regress & bootstrap, OK for commit? ChangeLog: 2018-01-16 Wilco Dijkstra * config/aarch64/aarch64.md (mov): Remove '*' in alternatives. (movsi_aarch64): Likewise. (load_pairsi): Likewise. (load_pairdi): Likewise. (store_pairsi): Likewise. (store_pairdi): Likewise. (load_pairsf): Likewise. (load_pairdf): Likewise. (store_pairsf): Likewise. (store_pairdf): Likewise. (zero_extend): Likewise. (fcvt_target): Add '?' to prefer w over r. gcc/testsuite/ * gcc.target/aarch64/vfp-1.c: Update test. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index e52e8350a203b288208c1acb12c8b881d5e8039a..088ed8cb0aad0be08a7e19064708ea14499230f2 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -907,8 +907,8 @@ (define_expand "mov" ) (define_insn "*mov_aarch64" - [(set (match_operand:SHORT 0 "nonimmediate_operand" "=r,r, *w,r ,r,*w, m, m, r,*w,*w") - (match_operand:SHORT 1 "aarch64_mov_operand" " r,M,D,Usv,m, m,rZ,*w,*w, r,*w"))] + [(set (match_operand:SHORT 0 "nonimmediate_operand" "=r,r, w,r ,r,w, m,m,r,w,w") + (match_operand:SHORT 1 "aarch64_mov_operand" " r,M,D,Usv,m,m,rZ,w,w,r,w"))] "(register_operand (operands[0], mode) || aarch64_reg_or_zero (operands[1], mode))" { @@ -974,7 +974,7 @@ (define_expand "mov" (define_insn_and_split "*movsi_aarch64" [(set (match_operand:SI 0 "nonimmediate_operand" "=r,k,r,r,r,r, r,w, m, m, r, r, w,r,w, w") - (match_operand:SI 1 "aarch64_mov_operand" " r,r,k,M,n,Usv,m,m,rZ,*w,Usa,Ush,rZ,w,w,Ds"))] + (match_operand:SI 1 "aarch64_mov_operand" " r,r,k,M,n,Usv,m,m,rZ,w,Usa,Ush,rZ,w,w,Ds"))] "(register_operand (operands[0], SImode) || aarch64_reg_or_zero (operands[1], SImode))" "@ @@ -1281,9 +1281,9 @@ (define_expand "movmemdi" ;; Operands 1 and 3 are tied together by the final condition; so we allow ;; fairly lax checking on the second memory operation. (define_insn "load_pairsi" - [(set (match_operand:SI 0 "register_operand" "=r,*w") + [(set (match_operand:SI 0 "register_operand" "=r,w") (match_operand:SI 1 "aarch64_mem_pair_operand" "Ump,Ump")) - (set (match_operand:SI 2 "register_operand" "=r,*w") + (set (match_operand:SI 2 "register_operand" "=r,w") (match_operand:SI 3 "memory_operand" "m,m"))] "rtx_equal_p (XEXP (operands[3], 0), plus_constant (Pmode, @@ -1297,9 +1297,9 @@ (define_insn "load_pairsi" ) (define_insn "load_pairdi" - [(set (match_operand:DI 0 "register_operand" "=r,*w") + [(set (match_operand:DI 0 "register_operand" "=r,w") (match_operand:DI 1 "aarch64_mem_pair_operand" "Ump,Ump")) - (set (match_operand:DI 2 "register_operand" "=r,*w") + (set (match_operand:DI 2 "register_operand" "=r,w") (match_operand:DI 3 "memory_operand" "m,m"))] "rtx_equal_p (XEXP (operands[3], 0), plus_constant (Pmode, @@ -1317,9 +1317,9 @@ (define_insn "load_pairdi" ;; fairly lax checking on the second memory operation. (define_insn "store_pairsi" [(set (match_operand:SI 0 "aarch64_mem_pair_operand" "=Ump,Ump") - (match_operand:SI 1 "aarch64_reg_or_zero" "rZ,*w")) + (match_operand:SI 1 "aarch64_reg_or_zero" "rZ,w")) (set (match_operand:SI 2 "memory_operand" "=m,m") - (match_operand:SI 3 "aarch64_reg_or_zero" "rZ,*w"))] + (match_operand:SI 3 "aarch64_reg_or_zero" "rZ,w"))] "rtx_equal_p (XEXP (operands[2], 0), plus_constant (Pmode, XEXP (operands[0], 0), @@ -1333,9 +1333,9 @@ (define_insn "store_pairsi" (define_insn "store_pairdi" [(set (match_operand:DI 0 "aarch64_mem_pair_operand" "=Ump,Ump") - (match_operand:DI 1 "aarch64_reg_or_zero" "rZ,*w")) + (match_operand:DI 1 "aarch64_reg_or_zero" "rZ,w")) (set (match_operand:DI 2 "memory_operand" "=m,m") - (match_operand:DI 3 "aarch64_reg_or_zero" "rZ,*w"))] + (match_operand:DI 3 "aarch64_reg_or_zero" "rZ,w"))] "rtx_equal_p (XEXP (operands[2], 0), plus_constant (Pmode, XEXP (operands[0], 0), @@ -1350,9 +1350,9 @@ (define_insn "store_pairdi" ;; Operands 1 and 3 are tied together by the final condition; so we allow ;; fairly lax checking on the second memory operation. (define_insn "load_pairsf" - [(set (match_operand:SF 0 "register_operand" "=w,*r") + [(set (match_operand:SF 0 "register_operand" "=w,r") (match_operand:SF 1 "aarch64_mem_pair_operand" "Ump,Ump")) - (set (match_operand:SF 2 "register_operand" "=w,*r") + (set (match_operand:SF 2 "register_operand" "=w,r") (match_operand:SF 3 "memory_operand" "m,m"))] "rtx_equal_p (XEXP (operands[3], 0), plus_constant (Pmode, @@ -1366,9 +1366,9 @@ (define_insn "load_pairsf" ) (define_insn "load_pairdf" - [(set (match_operand:DF 0 "register_operand" "=w,*r") + [(set (match_operand:DF 0 "register_operand" "=w,r") (match_operand:DF 1 "aarch64_mem_pair_operand" "Ump,Ump")) - (set (match_operand:DF 2 "register_operand" "=w,*r") + (set (match_operand:DF 2 "register_operand" "=w,r") (match_operand:DF 3 "memory_operand" "m,m"))] "rtx_equal_p (XEXP (operands[3], 0), plus_constant (Pmode, @@ -1385,9 +1385,9 @@ (define_insn "load_pairdf" ;; fairly lax checking on the second memory operation. (define_insn "store_pairsf" [(set (match_operand:SF 0 "aarch64_mem_pair_operand" "=Ump,Ump") - (match_operand:SF 1 "aarch64_reg_or_fp_zero" "w,*rY")) + (match_operand:SF 1 "aarch64_reg_or_fp_zero" "w,rY")) (set (match_operand:SF 2 "memory_operand" "=m,m") - (match_operand:SF 3 "aarch64_reg_or_fp_zero" "w,*rY"))] + (match_operand:SF 3 "aarch64_reg_or_fp_zero" "w,rY"))] "rtx_equal_p (XEXP (operands[2], 0), plus_constant (Pmode, XEXP (operands[0], 0), @@ -1401,9 +1401,9 @@ (define_insn "store_pairsf" (define_insn "store_pairdf" [(set (match_operand:DF 0 "aarch64_mem_pair_operand" "=Ump,Ump") - (match_operand:DF 1 "aarch64_reg_or_fp_zero" "w,*rY")) + (match_operand:DF 1 "aarch64_reg_or_fp_zero" "w,rY")) (set (match_operand:DF 2 "memory_operand" "=m,m") - (match_operand:DF 3 "aarch64_reg_or_fp_zero" "w,*rY"))] + (match_operand:DF 3 "aarch64_reg_or_fp_zero" "w,rY"))] "rtx_equal_p (XEXP (operands[2], 0), plus_constant (Pmode, XEXP (operands[0], 0), @@ -1554,7 +1554,7 @@ (define_insn "*extend2_aarch64" ) (define_insn "*zero_extend2_aarch64" - [(set (match_operand:GPI 0 "register_operand" "=r,r,*w") + [(set (match_operand:GPI 0 "register_operand" "=r,r,w") (zero_extend:GPI (match_operand:SHORT 1 "nonimmediate_operand" "r,m,m")))] "" "@ @@ -5088,7 +5088,7 @@ (define_insn "_trunc2" (define_insn "2" [(set (match_operand:GPF 0 "register_operand" "=w,w") - (FLOATUORS:GPF (match_operand: 1 "register_operand" "w,r")))] + (FLOATUORS:GPF (match_operand: 1 "register_operand" "w,?r")))] "TARGET_FLOAT" "@ cvtf\t%0, %1 diff --git a/gcc/testsuite/gcc.target/aarch64/vfp-1.c b/gcc/testsuite/gcc.target/aarch64/vfp-1.c index 79c571402cc1c5e3a8b6c71a30edb230a101e1a0..02609bb52bafd43803be29cf15225568f7713434 100644 --- a/gcc/testsuite/gcc.target/aarch64/vfp-1.c +++ b/gcc/testsuite/gcc.target/aarch64/vfp-1.c @@ -32,7 +32,7 @@ void test_sf() { /* { dg-final { scan-assembler "fsqrt\ts\[0-9\]*" } } */ f1 = sqrtf (f1); /* cmpsf */ - /* { dg-final { scan-assembler "fcmp\ts\[0-9\]*" } } */ + /* { dg-final { scan-assembler "fcmpe\ts\[0-9\]*" } } */ if (f1 < f2) cond1 = 1; else @@ -64,7 +64,7 @@ void test_df() { /* { dg-final { scan-assembler "fsqrt\td\[0-9\]*" } } */ d1 = sqrt (d1); /* cmpdf */ - /* { dg-final { scan-assembler "fcmp\td\[0-9\]*" } } */ + /* { dg-final { scan-assembler "fcmpe\td\[0-9\]*" } } */ if (d1 < d2) cond1 = 1; else @@ -82,13 +82,13 @@ void test_convert () { /* { dg-final { scan-assembler "fcvt\ts\[0-9\]*" } } */ f1 = d1; /* fixsfsi2 */ - /* { dg-final { scan-assembler "fcvtzs\tw\[0-9\], s\[0-9\]*" } } */ + /* { dg-final { scan-assembler "fcvtzs\ts\[0-9\], s\[0-9\]*" } } */ i1 = f1; /* fixdfsi2 */ /* { dg-final { scan-assembler "fcvtzs\tw\[0-9\], d\[0-9\]*" } } */ i1 = d1; /* fixunsfsi2 */ - /* { dg-final { scan-assembler "fcvtzu\tw\[0-9\], s\[0-9\]*" } } */ + /* { dg-final { scan-assembler "fcvtzu\ts\[0-9\], s\[0-9\]*" } } */ u1 = f1; /* fixunsdfsi2 */ /* { dg-final { scan-assembler "fcvtzu\tw\[0-9\], d\[0-9\]*" } } */