| Message ID | D2XS5BFE29KA.1QNVKQTSR936X@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | RISC-V: Error early with V and no M extension. [PR116036] | expand |
LGTM, although I was a little late to join the meeting yesterday, but I vaguely know you guys are discussing this, that combination really does not make too much sense and also the LLVM side already does the same thing :) On Wed, Jul 24, 2024 at 8:50 PM Robin Dapp <rdapp.gcc@gmail.com> wrote: > > Hi, > > for calculating the value of a poly_int at runtime we use a multiplication > instruction that requires the M extension. Instead of just asserting and > ICEing this patch emits an early error at option-parsing time. > > We have several tests that use only "i" (without "m") and I adjusted all of > them to "im". For now, I didn't verify if the original error just with "i" > still occurs but just added "m". > > Tested on rv64gcv_zvfh_zvbb. > > Regards > Robin > > gcc/ChangeLog: > > PR target/116036 > > * config/riscv/riscv.cc (riscv_override_options_internal): Error > with TARGET_VECTOR && !TARGET_MUL. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/base/pr116036.c: New test. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/arch-31.c: Add m to arch string and expect it. > * gcc.target/riscv/arch-32.c: Ditto. > * gcc.target/riscv/arch-37.c: Ditto. > * gcc.target/riscv/arch-38.c: Ditto. > * gcc.target/riscv/predef-14.c: Ditto. > * gcc.target/riscv/predef-15.c: Ditto. > * gcc.target/riscv/predef-16.c: Ditto. > * gcc.target/riscv/predef-26.c: Ditto. > * gcc.target/riscv/predef-27.c: Ditto. > * gcc.target/riscv/predef-32.c: Ditto. > * gcc.target/riscv/predef-33.c: Ditto. > * gcc.target/riscv/predef-36.c: Ditto. > * gcc.target/riscv/predef-37.c: Ditto. > * gcc.target/riscv/rvv/autovec/pr111486.c: Add m to arch string. > * gcc.target/riscv/compare-debug-1.c: Ditto. > * gcc.target/riscv/compare-debug-2.c: Ditto. > * gcc.target/riscv/rvv/base/pr116036.c: New test. > --- > gcc/config/riscv/riscv.cc | 5 +++++ > gcc/internal-fn.cc | 3 ++- > gcc/testsuite/gcc.target/riscv/arch-31.c | 2 +- > gcc/testsuite/gcc.target/riscv/arch-32.c | 2 +- > gcc/testsuite/gcc.target/riscv/arch-37.c | 2 +- > gcc/testsuite/gcc.target/riscv/arch-38.c | 2 +- > gcc/testsuite/gcc.target/riscv/compare-debug-1.c | 2 +- > gcc/testsuite/gcc.target/riscv/compare-debug-2.c | 2 +- > gcc/testsuite/gcc.target/riscv/predef-14.c | 6 +++--- > gcc/testsuite/gcc.target/riscv/predef-15.c | 4 ++-- > gcc/testsuite/gcc.target/riscv/predef-16.c | 4 ++-- > gcc/testsuite/gcc.target/riscv/predef-26.c | 6 +++++- > gcc/testsuite/gcc.target/riscv/predef-27.c | 6 +++++- > gcc/testsuite/gcc.target/riscv/predef-32.c | 6 +++++- > gcc/testsuite/gcc.target/riscv/predef-33.c | 6 +++++- > gcc/testsuite/gcc.target/riscv/predef-36.c | 6 +++++- > gcc/testsuite/gcc.target/riscv/predef-37.c | 6 +++++- > gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111486.c | 2 +- > gcc/testsuite/gcc.target/riscv/rvv/base/pr116036.c | 11 +++++++++++ > 19 files changed, 62 insertions(+), 21 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr116036.c > > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index ca9ea1b70f3..487698a8e4f 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -9690,6 +9690,11 @@ riscv_override_options_internal (struct gcc_options *opts) > else if (!TARGET_MUL_OPTS_P (opts) && TARGET_DIV_OPTS_P (opts)) > error ("%<-mdiv%> requires %<-march%> to subsume the %<M%> extension"); > > + /* We might use a multiplication to calculate the scalable vector length at > + runtime. Therefore, require the M extension. */ > + if (TARGET_VECTOR && !TARGET_MUL) > + sorry ("the %<V%> extension requires the %<M%> extension"); > + > /* Likewise floating-point division and square root. */ > if ((TARGET_HARD_FLOAT_OPTS_P (opts) || TARGET_ZFINX_OPTS_P (opts)) > && ((target_flags_explicit & MASK_FDIV) == 0)) > diff --git a/gcc/internal-fn.cc b/gcc/internal-fn.cc > index 826d552a6fd..eb6c033535c 100644 > --- a/gcc/internal-fn.cc > +++ b/gcc/internal-fn.cc > @@ -5049,7 +5049,8 @@ internal_len_load_store_bias (internal_fn ifn, machine_mode mode) > } > > /* Return true if the given ELS_VALUE is supported for a > - MASK_LOAD or MASK_LEN_LOAD with mode MODE. */ > + MASK_LOAD or MASK_LEN_LOAD with mode MODE. The target's > + preferred else value is return in ELSVAL. */ > > bool > internal_mask_load_else_supported_p (internal_fn ifn, > diff --git a/gcc/testsuite/gcc.target/riscv/arch-31.c b/gcc/testsuite/gcc.target/riscv/arch-31.c > index 5180753b905..9b867c5ecd2 100644 > --- a/gcc/testsuite/gcc.target/riscv/arch-31.c > +++ b/gcc/testsuite/gcc.target/riscv/arch-31.c > @@ -1,5 +1,5 @@ > /* { dg-do compile } */ > -/* { dg-options "-march=rv32i_zvfbfmin -mabi=ilp32f" } */ > +/* { dg-options "-march=rv32im_zvfbfmin -mabi=ilp32f" } */ > int foo() > { > } > diff --git a/gcc/testsuite/gcc.target/riscv/arch-32.c b/gcc/testsuite/gcc.target/riscv/arch-32.c > index 49616832512..49a3db79489 100644 > --- a/gcc/testsuite/gcc.target/riscv/arch-32.c > +++ b/gcc/testsuite/gcc.target/riscv/arch-32.c > @@ -1,5 +1,5 @@ > /* { dg-do compile } */ > -/* { dg-options "-march=rv64iv_zvfbfmin -mabi=lp64d" } */ > +/* { dg-options "-march=rv64imv_zvfbfmin -mabi=lp64d" } */ > int foo() > { > } > diff --git a/gcc/testsuite/gcc.target/riscv/arch-37.c b/gcc/testsuite/gcc.target/riscv/arch-37.c > index 5b19a73c556..b56ba77b973 100644 > --- a/gcc/testsuite/gcc.target/riscv/arch-37.c > +++ b/gcc/testsuite/gcc.target/riscv/arch-37.c > @@ -1,5 +1,5 @@ > /* { dg-do compile } */ > -/* { dg-options "-march=rv32i_zvfbfwma -mabi=ilp32f" } */ > +/* { dg-options "-march=rv32im_zvfbfwma -mabi=ilp32f" } */ > int > foo () > {} > diff --git a/gcc/testsuite/gcc.target/riscv/arch-38.c b/gcc/testsuite/gcc.target/riscv/arch-38.c > index cee3efebe75..164a91e38a3 100644 > --- a/gcc/testsuite/gcc.target/riscv/arch-38.c > +++ b/gcc/testsuite/gcc.target/riscv/arch-38.c > @@ -1,5 +1,5 @@ > /* { dg-do compile } */ > -/* { dg-options "-march=rv64iv_zvfbfwma -mabi=lp64d" } */ > +/* { dg-options "-march=rv64imv_zvfbfwma -mabi=lp64d" } */ > int > foo () > {} > diff --git a/gcc/testsuite/gcc.target/riscv/compare-debug-1.c b/gcc/testsuite/gcc.target/riscv/compare-debug-1.c > index d65bb287b9a..c22e967f03d 100644 > --- a/gcc/testsuite/gcc.target/riscv/compare-debug-1.c > +++ b/gcc/testsuite/gcc.target/riscv/compare-debug-1.c > @@ -1,5 +1,5 @@ > /* { dg-do compile } */ > -/* { dg-options "-O -fno-tree-ch --param=max-completely-peel-times=0 -march=rv64iv -mabi=lp64d -fcompare-debug" } */ > +/* { dg-options "-O -fno-tree-ch --param=max-completely-peel-times=0 -march=rv64imv -mabi=lp64d -fcompare-debug" } */ > > > void > diff --git a/gcc/testsuite/gcc.target/riscv/compare-debug-2.c b/gcc/testsuite/gcc.target/riscv/compare-debug-2.c > index d87758475e4..be9bda17b59 100644 > --- a/gcc/testsuite/gcc.target/riscv/compare-debug-2.c > +++ b/gcc/testsuite/gcc.target/riscv/compare-debug-2.c > @@ -1,3 +1,3 @@ > /* { dg-do compile } */ > -/* { dg-options "-O -fno-tree-ch --param=max-completely-peel-times=0 -march=rv64iv -mabi=lp64d -fno-dce -fschedule-insns -fcompare-debug" } */ > +/* { dg-options "-O -fno-tree-ch --param=max-completely-peel-times=0 -march=rv64imv -mabi=lp64d -fno-dce -fschedule-insns -fcompare-debug" } */ > #include "compare-debug-1.c" > diff --git a/gcc/testsuite/gcc.target/riscv/predef-14.c b/gcc/testsuite/gcc.target/riscv/predef-14.c > index 4815150ddfa..138209a0169 100644 > --- a/gcc/testsuite/gcc.target/riscv/predef-14.c > +++ b/gcc/testsuite/gcc.target/riscv/predef-14.c > @@ -1,5 +1,5 @@ > /* { dg-do compile } */ > -/* { dg-options "-march=rv32iv -mabi=ilp32 -mcmodel=medlow -misa-spec=2.2" } */ > +/* { dg-options "-march=rv32imv -mabi=ilp32 -mcmodel=medlow -misa-spec=2.2" } */ > > int main () { > > @@ -27,8 +27,8 @@ int main () { > #error "__riscv_a" > #endif > > -#if defined(__riscv_m) > -#error "__riscv_m" > +#if !defined(__riscv_mul) > +#error "__riscv_mul" > #endif > > #if !defined(__riscv_f) > diff --git a/gcc/testsuite/gcc.target/riscv/predef-15.c b/gcc/testsuite/gcc.target/riscv/predef-15.c > index dad14952ade..fd119dc7492 100644 > --- a/gcc/testsuite/gcc.target/riscv/predef-15.c > +++ b/gcc/testsuite/gcc.target/riscv/predef-15.c > @@ -1,5 +1,5 @@ > /* { dg-do compile } */ > -/* { dg-options "-march=rv64iv_zvl512b -mabi=lp64 -mcmodel=medlow -misa-spec=2.2" } */ > +/* { dg-options "-march=rv64imv_zvl512b -mabi=lp64 -mcmodel=medlow -misa-spec=2.2" } */ > > int main () { > > @@ -27,7 +27,7 @@ int main () { > #error "__riscv_a" > #endif > > -#if defined(__riscv_m) > +#if !defined(__riscv_m) > #error "__riscv_m" > #endif > > diff --git a/gcc/testsuite/gcc.target/riscv/predef-16.c b/gcc/testsuite/gcc.target/riscv/predef-16.c > index faebc1ab4f2..d64b8dc56eb 100644 > --- a/gcc/testsuite/gcc.target/riscv/predef-16.c > +++ b/gcc/testsuite/gcc.target/riscv/predef-16.c > @@ -1,5 +1,5 @@ > /* { dg-do compile } */ > -/* { dg-options "-march=rv64i_zve64f -mabi=lp64 -mcmodel=medlow -misa-spec=2.2" } */ > +/* { dg-options "-march=rv64im_zve64f -mabi=lp64 -mcmodel=medlow -misa-spec=2.2" } */ > > int main () { > > @@ -27,7 +27,7 @@ int main () { > #error "__riscv_a" > #endif > > -#if defined(__riscv_m) > +#if !defined(__riscv_m) > #error "__riscv_m" > #endif > > diff --git a/gcc/testsuite/gcc.target/riscv/predef-26.c b/gcc/testsuite/gcc.target/riscv/predef-26.c > index 285f64bd6c0..df0f05e4550 100644 > --- a/gcc/testsuite/gcc.target/riscv/predef-26.c > +++ b/gcc/testsuite/gcc.target/riscv/predef-26.c > @@ -1,5 +1,5 @@ > /* { dg-do compile } */ > -/* { dg-options "-O2 -march=rv64i_zvfhmin -mabi=lp64f -mcmodel=medlow -misa-spec=20191213" } */ > +/* { dg-options "-O2 -march=rv64im_zvfhmin -mabi=lp64f -mcmodel=medlow -misa-spec=20191213" } */ > > int main () { > > @@ -15,6 +15,10 @@ int main () { > #error "__riscv_i" > #endif > > +#if !defined(__riscv_m) > +#error "__riscv_m" > +#endif > + > #if !defined(__riscv_f) > #error "__riscv_f" > #endif > diff --git a/gcc/testsuite/gcc.target/riscv/predef-27.c b/gcc/testsuite/gcc.target/riscv/predef-27.c > index 0f9ab4417a6..554acf36e5c 100644 > --- a/gcc/testsuite/gcc.target/riscv/predef-27.c > +++ b/gcc/testsuite/gcc.target/riscv/predef-27.c > @@ -1,5 +1,5 @@ > /* { dg-do compile } */ > -/* { dg-options "-O2 -march=rv64i_zvfh -mabi=lp64f -mcmodel=medlow -misa-spec=20191213" } */ > +/* { dg-options "-O2 -march=rv64im_zvfh -mabi=lp64f -mcmodel=medlow -misa-spec=20191213" } */ > > int main () { > > @@ -15,6 +15,10 @@ int main () { > #error "__riscv_i" > #endif > > +#if !defined(__riscv_m) > +#error "__riscv_m" > +#endif > + > #if !defined(__riscv_f) > #error "__riscv_f" > #endif > diff --git a/gcc/testsuite/gcc.target/riscv/predef-32.c b/gcc/testsuite/gcc.target/riscv/predef-32.c > index 7417e0d996f..6d56f8fe6b8 100644 > --- a/gcc/testsuite/gcc.target/riscv/predef-32.c > +++ b/gcc/testsuite/gcc.target/riscv/predef-32.c > @@ -1,5 +1,5 @@ > /* { dg-do compile } */ > -/* { dg-options "-O2 -march=rv32i_zvfbfmin -mabi=ilp32f -mcmodel=medlow -misa-spec=20191213" } */ > +/* { dg-options "-O2 -march=rv32im_zvfbfmin -mabi=ilp32f -mcmodel=medlow -misa-spec=20191213" } */ > > int main () { > > @@ -15,6 +15,10 @@ int main () { > #error "__riscv_i" > #endif > > +#if !defined(__riscv_m) > +#error "__riscv_m" > +#endif > + > #if !defined(__riscv_f) > #error "__riscv_f" > #endif > diff --git a/gcc/testsuite/gcc.target/riscv/predef-33.c b/gcc/testsuite/gcc.target/riscv/predef-33.c > index 74d05bc9719..f1da7e582af 100644 > --- a/gcc/testsuite/gcc.target/riscv/predef-33.c > +++ b/gcc/testsuite/gcc.target/riscv/predef-33.c > @@ -1,5 +1,5 @@ > /* { dg-do compile } */ > -/* { dg-options "-O2 -march=rv64iv_zvfbfmin -mabi=lp64d -mcmodel=medlow -misa-spec=20191213" } */ > +/* { dg-options "-O2 -march=rv64imv_zvfbfmin -mabi=lp64d -mcmodel=medlow -misa-spec=20191213" } */ > > int main () { > > @@ -15,6 +15,10 @@ int main () { > #error "__riscv_i" > #endif > > +#if !defined(__riscv_m) > +#error "__riscv_m" > +#endif > + > #if !defined(__riscv_f) > #error "__riscv_f" > #endif > diff --git a/gcc/testsuite/gcc.target/riscv/predef-36.c b/gcc/testsuite/gcc.target/riscv/predef-36.c > index b0205b08513..7c87a42f3d3 100644 > --- a/gcc/testsuite/gcc.target/riscv/predef-36.c > +++ b/gcc/testsuite/gcc.target/riscv/predef-36.c > @@ -1,5 +1,5 @@ > /* { dg-do compile } */ > -/* { dg-options "-O2 -march=rv32i_zvfbfwma -mabi=ilp32f -mcmodel=medlow -misa-spec=20191213" } */ > +/* { dg-options "-O2 -march=rv32im_zvfbfwma -mabi=ilp32f -mcmodel=medlow -misa-spec=20191213" } */ > > int > main () > @@ -16,6 +16,10 @@ main () > #error "__riscv_i" > #endif > > +#if !defined(__riscv_m) > +#error "__riscv_m" > +#endif > + > #if !defined(__riscv_f) > #error "__riscv_f" > #endif > diff --git a/gcc/testsuite/gcc.target/riscv/predef-37.c b/gcc/testsuite/gcc.target/riscv/predef-37.c > index b5aa41102f4..150150e3246 100644 > --- a/gcc/testsuite/gcc.target/riscv/predef-37.c > +++ b/gcc/testsuite/gcc.target/riscv/predef-37.c > @@ -1,5 +1,5 @@ > /* { dg-do compile } */ > -/* { dg-options "-O2 -march=rv64iv_zvfbfwma -mabi=lp64d -mcmodel=medlow -misa-spec=20191213" } */ > +/* { dg-options "-O2 -march=rv64imv_zvfbfwma -mabi=lp64d -mcmodel=medlow -misa-spec=20191213" } */ > > int > main () > @@ -16,6 +16,10 @@ main () > #error "__riscv_i" > #endif > > +#if !defined(__riscv_m) > +#error "__riscv_m" > +#endif > + > #if !defined(__riscv_f) > #error "__riscv_f" > #endif > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111486.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111486.c > index 2ba2a363399..483e9b931f6 100644 > --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111486.c > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111486.c > @@ -1,5 +1,5 @@ > /* { dg-do compile } */ > -/* { dg-options "-march=rv64iv -mabi=lp64d -O2" } */ > +/* { dg-options "-march=rv64imv -mabi=lp64d -O2" } */ > > typedef char __attribute__((__vector_size__ (1))) V; > > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr116036.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr116036.c > new file mode 100644 > index 00000000000..6819a786aec > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr116036.c > @@ -0,0 +1,11 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv64idv -mabi=lp64d -O3" } */ > + > +int a[15][15]; > +void init() { > + for (int i_0 ; i_0 < 15 ; ++i_0) > + for (int i_1 = 0; i_1 < 15; ++i_1) > + a[i_0][i_1] = 1; > +} > + > +/* { dg-excess-errors "sorry, unimplemented: the 'V' extension requires the 'M' extension" } */ > -- > 2.45.2 >
On 7/24/24 7:54 AM, Kito Cheng wrote: > LGTM, although I was a little late to join the meeting yesterday, but > I vaguely know you guys are discussing this, that combination really > does not make too much sense and also the LLVM side already does the > same thing :) Yea, the idea was this combination doesn't make sense and we should issue a gracefull diagnostic. If some oddball implementation comes along, the implementors of that oddball implementation can deal with this problem. jeff
> diff --git a/gcc/internal-fn.cc b/gcc/internal-fn.cc > index 826d552a6fd..eb6c033535c 100644 > --- a/gcc/internal-fn.cc > +++ b/gcc/internal-fn.cc > @@ -5049,7 +5049,8 @@ internal_len_load_store_bias (internal_fn ifn, machine_mode mode) > } > > /* Return true if the given ELS_VALUE is supported for a > - MASK_LOAD or MASK_LEN_LOAD with mode MODE. */ > + MASK_LOAD or MASK_LEN_LOAD with mode MODE. The target's > + preferred else value is return in ELSVAL. */ Grml, this is obviously not part of this patch but a rebase error. Going to send a V2.
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index ca9ea1b70f3..487698a8e4f 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -9690,6 +9690,11 @@ riscv_override_options_internal (struct gcc_options *opts) else if (!TARGET_MUL_OPTS_P (opts) && TARGET_DIV_OPTS_P (opts)) error ("%<-mdiv%> requires %<-march%> to subsume the %<M%> extension"); + /* We might use a multiplication to calculate the scalable vector length at + runtime. Therefore, require the M extension. */ + if (TARGET_VECTOR && !TARGET_MUL) + sorry ("the %<V%> extension requires the %<M%> extension"); + /* Likewise floating-point division and square root. */ if ((TARGET_HARD_FLOAT_OPTS_P (opts) || TARGET_ZFINX_OPTS_P (opts)) && ((target_flags_explicit & MASK_FDIV) == 0)) diff --git a/gcc/internal-fn.cc b/gcc/internal-fn.cc index 826d552a6fd..eb6c033535c 100644 --- a/gcc/internal-fn.cc +++ b/gcc/internal-fn.cc @@ -5049,7 +5049,8 @@ internal_len_load_store_bias (internal_fn ifn, machine_mode mode) } /* Return true if the given ELS_VALUE is supported for a - MASK_LOAD or MASK_LEN_LOAD with mode MODE. */ + MASK_LOAD or MASK_LEN_LOAD with mode MODE. The target's + preferred else value is return in ELSVAL. */ bool internal_mask_load_else_supported_p (internal_fn ifn, diff --git a/gcc/testsuite/gcc.target/riscv/arch-31.c b/gcc/testsuite/gcc.target/riscv/arch-31.c index 5180753b905..9b867c5ecd2 100644 --- a/gcc/testsuite/gcc.target/riscv/arch-31.c +++ b/gcc/testsuite/gcc.target/riscv/arch-31.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32i_zvfbfmin -mabi=ilp32f" } */ +/* { dg-options "-march=rv32im_zvfbfmin -mabi=ilp32f" } */ int foo() { } diff --git a/gcc/testsuite/gcc.target/riscv/arch-32.c b/gcc/testsuite/gcc.target/riscv/arch-32.c index 49616832512..49a3db79489 100644 --- a/gcc/testsuite/gcc.target/riscv/arch-32.c +++ b/gcc/testsuite/gcc.target/riscv/arch-32.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64iv_zvfbfmin -mabi=lp64d" } */ +/* { dg-options "-march=rv64imv_zvfbfmin -mabi=lp64d" } */ int foo() { } diff --git a/gcc/testsuite/gcc.target/riscv/arch-37.c b/gcc/testsuite/gcc.target/riscv/arch-37.c index 5b19a73c556..b56ba77b973 100644 --- a/gcc/testsuite/gcc.target/riscv/arch-37.c +++ b/gcc/testsuite/gcc.target/riscv/arch-37.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32i_zvfbfwma -mabi=ilp32f" } */ +/* { dg-options "-march=rv32im_zvfbfwma -mabi=ilp32f" } */ int foo () {} diff --git a/gcc/testsuite/gcc.target/riscv/arch-38.c b/gcc/testsuite/gcc.target/riscv/arch-38.c index cee3efebe75..164a91e38a3 100644 --- a/gcc/testsuite/gcc.target/riscv/arch-38.c +++ b/gcc/testsuite/gcc.target/riscv/arch-38.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64iv_zvfbfwma -mabi=lp64d" } */ +/* { dg-options "-march=rv64imv_zvfbfwma -mabi=lp64d" } */ int foo () {} diff --git a/gcc/testsuite/gcc.target/riscv/compare-debug-1.c b/gcc/testsuite/gcc.target/riscv/compare-debug-1.c index d65bb287b9a..c22e967f03d 100644 --- a/gcc/testsuite/gcc.target/riscv/compare-debug-1.c +++ b/gcc/testsuite/gcc.target/riscv/compare-debug-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O -fno-tree-ch --param=max-completely-peel-times=0 -march=rv64iv -mabi=lp64d -fcompare-debug" } */ +/* { dg-options "-O -fno-tree-ch --param=max-completely-peel-times=0 -march=rv64imv -mabi=lp64d -fcompare-debug" } */ void diff --git a/gcc/testsuite/gcc.target/riscv/compare-debug-2.c b/gcc/testsuite/gcc.target/riscv/compare-debug-2.c index d87758475e4..be9bda17b59 100644 --- a/gcc/testsuite/gcc.target/riscv/compare-debug-2.c +++ b/gcc/testsuite/gcc.target/riscv/compare-debug-2.c @@ -1,3 +1,3 @@ /* { dg-do compile } */ -/* { dg-options "-O -fno-tree-ch --param=max-completely-peel-times=0 -march=rv64iv -mabi=lp64d -fno-dce -fschedule-insns -fcompare-debug" } */ +/* { dg-options "-O -fno-tree-ch --param=max-completely-peel-times=0 -march=rv64imv -mabi=lp64d -fno-dce -fschedule-insns -fcompare-debug" } */ #include "compare-debug-1.c" diff --git a/gcc/testsuite/gcc.target/riscv/predef-14.c b/gcc/testsuite/gcc.target/riscv/predef-14.c index 4815150ddfa..138209a0169 100644 --- a/gcc/testsuite/gcc.target/riscv/predef-14.c +++ b/gcc/testsuite/gcc.target/riscv/predef-14.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32iv -mabi=ilp32 -mcmodel=medlow -misa-spec=2.2" } */ +/* { dg-options "-march=rv32imv -mabi=ilp32 -mcmodel=medlow -misa-spec=2.2" } */ int main () { @@ -27,8 +27,8 @@ int main () { #error "__riscv_a" #endif -#if defined(__riscv_m) -#error "__riscv_m" +#if !defined(__riscv_mul) +#error "__riscv_mul" #endif #if !defined(__riscv_f) diff --git a/gcc/testsuite/gcc.target/riscv/predef-15.c b/gcc/testsuite/gcc.target/riscv/predef-15.c index dad14952ade..fd119dc7492 100644 --- a/gcc/testsuite/gcc.target/riscv/predef-15.c +++ b/gcc/testsuite/gcc.target/riscv/predef-15.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64iv_zvl512b -mabi=lp64 -mcmodel=medlow -misa-spec=2.2" } */ +/* { dg-options "-march=rv64imv_zvl512b -mabi=lp64 -mcmodel=medlow -misa-spec=2.2" } */ int main () { @@ -27,7 +27,7 @@ int main () { #error "__riscv_a" #endif -#if defined(__riscv_m) +#if !defined(__riscv_m) #error "__riscv_m" #endif diff --git a/gcc/testsuite/gcc.target/riscv/predef-16.c b/gcc/testsuite/gcc.target/riscv/predef-16.c index faebc1ab4f2..d64b8dc56eb 100644 --- a/gcc/testsuite/gcc.target/riscv/predef-16.c +++ b/gcc/testsuite/gcc.target/riscv/predef-16.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64i_zve64f -mabi=lp64 -mcmodel=medlow -misa-spec=2.2" } */ +/* { dg-options "-march=rv64im_zve64f -mabi=lp64 -mcmodel=medlow -misa-spec=2.2" } */ int main () { @@ -27,7 +27,7 @@ int main () { #error "__riscv_a" #endif -#if defined(__riscv_m) +#if !defined(__riscv_m) #error "__riscv_m" #endif diff --git a/gcc/testsuite/gcc.target/riscv/predef-26.c b/gcc/testsuite/gcc.target/riscv/predef-26.c index 285f64bd6c0..df0f05e4550 100644 --- a/gcc/testsuite/gcc.target/riscv/predef-26.c +++ b/gcc/testsuite/gcc.target/riscv/predef-26.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -march=rv64i_zvfhmin -mabi=lp64f -mcmodel=medlow -misa-spec=20191213" } */ +/* { dg-options "-O2 -march=rv64im_zvfhmin -mabi=lp64f -mcmodel=medlow -misa-spec=20191213" } */ int main () { @@ -15,6 +15,10 @@ int main () { #error "__riscv_i" #endif +#if !defined(__riscv_m) +#error "__riscv_m" +#endif + #if !defined(__riscv_f) #error "__riscv_f" #endif diff --git a/gcc/testsuite/gcc.target/riscv/predef-27.c b/gcc/testsuite/gcc.target/riscv/predef-27.c index 0f9ab4417a6..554acf36e5c 100644 --- a/gcc/testsuite/gcc.target/riscv/predef-27.c +++ b/gcc/testsuite/gcc.target/riscv/predef-27.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -march=rv64i_zvfh -mabi=lp64f -mcmodel=medlow -misa-spec=20191213" } */ +/* { dg-options "-O2 -march=rv64im_zvfh -mabi=lp64f -mcmodel=medlow -misa-spec=20191213" } */ int main () { @@ -15,6 +15,10 @@ int main () { #error "__riscv_i" #endif +#if !defined(__riscv_m) +#error "__riscv_m" +#endif + #if !defined(__riscv_f) #error "__riscv_f" #endif diff --git a/gcc/testsuite/gcc.target/riscv/predef-32.c b/gcc/testsuite/gcc.target/riscv/predef-32.c index 7417e0d996f..6d56f8fe6b8 100644 --- a/gcc/testsuite/gcc.target/riscv/predef-32.c +++ b/gcc/testsuite/gcc.target/riscv/predef-32.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -march=rv32i_zvfbfmin -mabi=ilp32f -mcmodel=medlow -misa-spec=20191213" } */ +/* { dg-options "-O2 -march=rv32im_zvfbfmin -mabi=ilp32f -mcmodel=medlow -misa-spec=20191213" } */ int main () { @@ -15,6 +15,10 @@ int main () { #error "__riscv_i" #endif +#if !defined(__riscv_m) +#error "__riscv_m" +#endif + #if !defined(__riscv_f) #error "__riscv_f" #endif diff --git a/gcc/testsuite/gcc.target/riscv/predef-33.c b/gcc/testsuite/gcc.target/riscv/predef-33.c index 74d05bc9719..f1da7e582af 100644 --- a/gcc/testsuite/gcc.target/riscv/predef-33.c +++ b/gcc/testsuite/gcc.target/riscv/predef-33.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -march=rv64iv_zvfbfmin -mabi=lp64d -mcmodel=medlow -misa-spec=20191213" } */ +/* { dg-options "-O2 -march=rv64imv_zvfbfmin -mabi=lp64d -mcmodel=medlow -misa-spec=20191213" } */ int main () { @@ -15,6 +15,10 @@ int main () { #error "__riscv_i" #endif +#if !defined(__riscv_m) +#error "__riscv_m" +#endif + #if !defined(__riscv_f) #error "__riscv_f" #endif diff --git a/gcc/testsuite/gcc.target/riscv/predef-36.c b/gcc/testsuite/gcc.target/riscv/predef-36.c index b0205b08513..7c87a42f3d3 100644 --- a/gcc/testsuite/gcc.target/riscv/predef-36.c +++ b/gcc/testsuite/gcc.target/riscv/predef-36.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -march=rv32i_zvfbfwma -mabi=ilp32f -mcmodel=medlow -misa-spec=20191213" } */ +/* { dg-options "-O2 -march=rv32im_zvfbfwma -mabi=ilp32f -mcmodel=medlow -misa-spec=20191213" } */ int main () @@ -16,6 +16,10 @@ main () #error "__riscv_i" #endif +#if !defined(__riscv_m) +#error "__riscv_m" +#endif + #if !defined(__riscv_f) #error "__riscv_f" #endif diff --git a/gcc/testsuite/gcc.target/riscv/predef-37.c b/gcc/testsuite/gcc.target/riscv/predef-37.c index b5aa41102f4..150150e3246 100644 --- a/gcc/testsuite/gcc.target/riscv/predef-37.c +++ b/gcc/testsuite/gcc.target/riscv/predef-37.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -march=rv64iv_zvfbfwma -mabi=lp64d -mcmodel=medlow -misa-spec=20191213" } */ +/* { dg-options "-O2 -march=rv64imv_zvfbfwma -mabi=lp64d -mcmodel=medlow -misa-spec=20191213" } */ int main () @@ -16,6 +16,10 @@ main () #error "__riscv_i" #endif +#if !defined(__riscv_m) +#error "__riscv_m" +#endif + #if !defined(__riscv_f) #error "__riscv_f" #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111486.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111486.c index 2ba2a363399..483e9b931f6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111486.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111486.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64iv -mabi=lp64d -O2" } */ +/* { dg-options "-march=rv64imv -mabi=lp64d -O2" } */ typedef char __attribute__((__vector_size__ (1))) V; diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr116036.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr116036.c new file mode 100644 index 00000000000..6819a786aec --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr116036.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64idv -mabi=lp64d -O3" } */ + +int a[15][15]; +void init() { + for (int i_0 ; i_0 < 15 ; ++i_0) + for (int i_1 = 0; i_1 < 15; ++i_1) + a[i_0][i_1] = 1; +} + +/* { dg-excess-errors "sorry, unimplemented: the 'V' extension requires the 'M' extension" } */