From patchwork Fri Oct 10 07:58:57 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Evgeny Stupachenko X-Patchwork-Id: 398475 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id BC7CD1400DE for ; Fri, 10 Oct 2014 18:59:08 +1100 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:date:message-id:subject:from:to:content-type :content-transfer-encoding; q=dns; s=default; b=XeKzNqrVZiE9fs0a flJtjlQZr4SVeN8OpYIBKF4ub7GFwIUc2qMwR3bPIdIZrxZ+d3K4JOuBhT/n26G9 pDHVFSNO03531iVmLOd3o57ZODiQ/BOPV5b/jsuo5IBvNjTgR6L/0YcTsBgINpNH w1GlGDqKZ1sd1bj2EThusx2ha/8= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:date:message-id:subject:from:to:content-type :content-transfer-encoding; s=default; bh=PhUy/jk1pyvNS4eKMJU+GG r0IgE=; b=A9YdAqMva/COXnA2Vy2oEsvScHWk15ZnZBZ4zu3kuZitShIfcuKmP5 pHSYTPyvXK33QHRdHcC/LuZ0QTvgVqn3prIflu28K7+nQ/6TxhSWGTgVXsOqELGs sQTNswrS1qLGiDnOHUZuxFKAsiPhLiM4GbDIMSxCDb3gu3ly1y9ks= Received: (qmail 21126 invoked by alias); 10 Oct 2014 07:59:02 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 21113 invoked by uid 89); 10 Oct 2014 07:59:01 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.5 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-ig0-f178.google.com Received: from mail-ig0-f178.google.com (HELO mail-ig0-f178.google.com) (209.85.213.178) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Fri, 10 Oct 2014 07:58:59 +0000 Received: by mail-ig0-f178.google.com with SMTP id h3so1752273igd.5 for ; Fri, 10 Oct 2014 00:58:57 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.50.66.229 with SMTP id i5mr4216937igt.27.1412927937410; Fri, 10 Oct 2014 00:58:57 -0700 (PDT) Received: by 10.107.6.95 with HTTP; Fri, 10 Oct 2014 00:58:57 -0700 (PDT) Date: Fri, 10 Oct 2014 11:58:57 +0400 Message-ID: Subject: [PATCH 3/X, i386, PR54232] Enable EBX for x86 in 32bits PIC code From: Evgeny Stupachenko To: Jeff Law , vmakarov@redhat.com, Uros Bizjak , GCC Patches X-IsSubscribed: yes the patch improves performance when previous are applied. It makes RTL loop invariant behavior for GOT loads same as it was before the 2 previous patches. It improves 164.gzip (+9%), 253.perlbmk (+2%) giving ~0.5% to SPEC2000int (compiled with “-m32 -Ofast -flto -funroll-loops -fPIC” For example in 164.gzip. Before enabling EBX: loop begin: (I) 1. SI162 = prev (global address) 2. SI163 = SI142 & 0xfff (SI 142 modified in the loop) 3. SI164 = EBX + SI162 4. HI107 = SI163*2 + SI164 5. SI142 = HI107 Only INSN 1. treated as invariant and later combine propagates 2,3,4 into 5. After enabling EBX: loop begin: (I) 1. SI163 = prev (global address) 2. SI164 = SI142 & 0xfff (SI 142 modified in the loop) (I) 3. SI165 = SI143 + SI163 4. HI107 = SI164*2 + SI165 5. SI142 = HI107 INSNs 1. and 3. are treated as invariants (143 is GOT register) and hoisted outside the loop After that combine pass was unable to combine INSNs inside and outside the loop, which lead to higher register pressure and therefore new spills/fills. The patch fixes x86 address cost so that cost for addresses with GOT register becomes less, how it was before enabling EBX. In x86_address_cost the result of “REGNO (parts.base) >= FIRST_PSEUDO_REGISTER” for hard ebx was always false. The patch makes condition result the same when parts.base is GOT register (the same for parts.index). 2014-10-08 Evgeny Stupachenko * gcc/config/i386/i386.c (ix86_address_cost): Lower cost for when address contains GOT register. cost++; diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index b43e870..9d8cfd1 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -12497,8 +12497,12 @@ ix86_address_cost (rtx x, enum machine_mode, addr_space_t, bool) cost++; if (parts.base + && (!pic_offset_table_rtx + || REGNO (pic_offset_table_rtx) != REGNO(parts.base)) && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER) && parts.index + && (!pic_offset_table_rtx + || REGNO (pic_offset_table_rtx) != REGNO(parts.index)) && (!REG_P (parts.index) || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER) && parts.base != parts.index)