From patchwork Thu Jul 28 20:15:04 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 107380 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 95E6EB6F6F for ; Fri, 29 Jul 2011 22:09:45 +1000 (EST) Received: (qmail 10909 invoked by alias); 29 Jul 2011 12:09:42 -0000 Received: (qmail 10899 invoked by uid 22791); 29 Jul 2011 12:09:39 -0000 X-SWARE-Spam-Status: No, hits=-2.3 required=5.0 tests=AWL, BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, TW_OV, TW_ZJ X-Spam-Check-By: sourceware.org Received: from mail-qw0-f47.google.com (HELO mail-qw0-f47.google.com) (209.85.216.47) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Fri, 29 Jul 2011 12:09:25 +0000 Received: by qwh5 with SMTP id 5so2085214qwh.20 for ; Fri, 29 Jul 2011 05:09:24 -0700 (PDT) MIME-Version: 1.0 Received: by 10.229.118.69 with SMTP id u5mr365696qcq.122.1311884104368; Thu, 28 Jul 2011 13:15:04 -0700 (PDT) Received: by 10.229.98.193 with HTTP; Thu, 28 Jul 2011 13:15:04 -0700 (PDT) In-Reply-To: References: <20110728031121.GA11273@intel.com> Date: Thu, 28 Jul 2011 13:15:04 -0700 Message-ID: Subject: Re: PATCH: PR target/47715: [x32] Use SImode for thread pointer From: "H.J. Lu" To: Uros Bizjak Cc: gcc-patches@gcc.gnu.org X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org On Thu, Jul 28, 2011 at 11:31 AM, Uros Bizjak wrote: > On Thu, Jul 28, 2011 at 8:30 PM, H.J. Lu wrote: > >>>>>> TP is 32bit in x32  For load_tp_x32, we load SImode value and >>>>>> zero-extend to DImode. For add_tp_x32, we are adding SImode >>>>>> value.  We can't pretend TP is 64bit.  load_tp_x32 and add_tp_x32 >>>>>> must take SImode TP. >>>>>> >>>>> >>>>> I will see what I can do. >>>>> >>>> >>>> Here is the updated patch to use 32bit TP for 32. >>> >>> Why?? >>> >>> This part makes no sense: >>> >>> -  tp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TP); >>> +  tp = gen_rtx_UNSPEC (ptr_mode, gen_rtvec (1, const0_rtx), UNSPEC_TP); >>> +  if (ptr_mode != Pmode) >>> +    tp = convert_to_mode (Pmode, tp, 1); >>> >>> You will create zero_extend (unspec ...), that won't be matched by any pattern. >> >> No.  I created  zero_exten from (reg:SI) to (reg: DI). >> >>> Can you please explain, how is this pattern different than DImode >>> pattern, proposed in my patch? >>> >>> +(define_insn "*load_tp_x32" >>> +  [(set (match_operand:SI 0 "register_operand" "=r") >>> +       (unspec:SI [(const_int 0)] UNSPEC_TP))] >>> +  "TARGET_X32" >>> +  "mov{l}\t{%%fs:0, %0|%0, DWORD PTR fs:0}" >>> +  [(set_attr "type" "imov") >>> +   (set_attr "modrm" "0") >>> +   (set_attr "length" "7") >>> +   (set_attr "memory" "load") >>> +   (set_attr "imm_disp" "false")]) >>> >>> vs: >>> >>> +(define_insn "*load_tp_x32" >>> +  [(set (match_operand:DI 0 "register_operand" "=r") >>> +       (unspec:DI [(const_int 0)] UNSPEC_TP))] >> >> That is wrong since source (TP)  is 32bit.  This pattern tells compiler >> source is 64bit. > > Where? > Here is the revised patch. The difference is I changed *add_tp_x32 to SImode. For --- extern __thread int __libc_errno __attribute__ ((tls_model ("initial-exec"))); int * __errno_location (void) { return &__libc_errno; } --- compiled with -mx32 -O2 -fPIC DImode *add_tp_x32 generates: movq __libc_errno@gottpoff(%rip), %rax addl %fs:0, %eax mov %eax, %eax ret SImode *add_tp_x32 generates: movl %fs:0, %eax addl __libc_errno@gottpoff(%rip), %eax ret OK for trunk? Thanks. 2011-07-28 Uros Bizjak H.J. Lu PR target/47715 * config/i386/i386.md (*load_tp_x32): New. (*add_tp_x32): Likewise. (*load_tp_): Disabled for TARGET_X32. (*add_tp_): Likewise. diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index f33b8a0..7658522 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -12444,10 +12452,21 @@ (define_mode_attr tp_seg [(SI "gs") (DI "fs")]) ;; Load and add the thread base pointer from %:0. +(define_insn "*load_tp_x32" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(const_int 0)] UNSPEC_TP))] + "TARGET_X32" + "mov{l}\t{%%fs:0, %k0|%k0, DWORD PTR fs:0}" + [(set_attr "type" "imov") + (set_attr "modrm" "0") + (set_attr "length" "7") + (set_attr "memory" "load") + (set_attr "imm_disp" "false")]) + (define_insn "*load_tp_" [(set (match_operand:P 0 "register_operand" "=r") (unspec:P [(const_int 0)] UNSPEC_TP))] - "" + "!TARGET_X32" "mov{}\t{%%:0, %0|%0, PTR :0}" [(set_attr "type" "imov") (set_attr "modrm" "0") @@ -12455,12 +12474,25 @@ (set_attr "memory" "load") (set_attr "imm_disp" "false")]) +(define_insn "*add_tp_x32" + [(set (match_operand:SI 0 "register_operand" "=r") + (plus:SI (unspec:SI [(const_int 0)] UNSPEC_TP) + (match_operand:SI 1 "register_operand" "0"))) + (clobber (reg:CC FLAGS_REG))] + "TARGET_X32" + "add{l}\t{%%fs:0, %0|%0, DWORD PTR fs:0}" + [(set_attr "type" "alu") + (set_attr "modrm" "0") + (set_attr "length" "7") + (set_attr "memory" "load") + (set_attr "imm_disp" "false")]) + (define_insn "*add_tp_" [(set (match_operand:P 0 "register_operand" "=r") (plus:P (unspec:P [(const_int 0)] UNSPEC_TP) (match_operand:P 1 "register_operand" "0"))) (clobber (reg:CC FLAGS_REG))] - "" + "!TARGET_X32" "add{}\t{%%:0, %0|%0, PTR :0}" [(set_attr "type" "alu") (set_attr "modrm" "0")