From patchwork Wed Jul 20 01:16:19 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 105563 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id C78A9B6F71 for ; Wed, 20 Jul 2011 11:17:03 +1000 (EST) Received: (qmail 26994 invoked by alias); 20 Jul 2011 01:17:01 -0000 Received: (qmail 26981 invoked by uid 22791); 20 Jul 2011 01:17:00 -0000 X-SWARE-Spam-Status: No, hits=-2.3 required=5.0 tests=AWL, BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, TW_VZ, TW_ZB X-Spam-Check-By: sourceware.org Received: from mail-qy0-f175.google.com (HELO mail-qy0-f175.google.com) (209.85.216.175) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Wed, 20 Jul 2011 01:16:20 +0000 Received: by qyk30 with SMTP id 30so2497708qyk.20 for ; Tue, 19 Jul 2011 18:16:19 -0700 (PDT) MIME-Version: 1.0 Received: by 10.229.27.198 with SMTP id j6mr6545131qcc.10.1311124579632; Tue, 19 Jul 2011 18:16:19 -0700 (PDT) Received: by 10.229.190.16 with HTTP; Tue, 19 Jul 2011 18:16:19 -0700 (PDT) In-Reply-To: <4E25BE14.8010306@redhat.com> References: <20110719044537.GA3605@intel.com> <4E25BAF5.1000900@redhat.com> <4E25BE14.8010306@redhat.com> Date: Tue, 19 Jul 2011 18:16:19 -0700 Message-ID: Subject: Re: PATCH [7/n] X32: Handle address output and calls patterns From: "H.J. Lu" To: Richard Henderson Cc: gcc-patches@gcc.gnu.org, Uros Bizjak X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org On Tue, Jul 19, 2011 at 10:25 AM, Richard Henderson wrote: > On 07/19/2011 10:18 AM, H.J. Lu wrote: >> I had it in my x32 tree. But I reverted: >> >> http://gcc.gnu.org/ml/gcc-patches/2011-02/msg00954.html >> >> since Pmode is used in non-PIC tablejump, we have to put 64bit value for >> labels with 0 upper 32bits in tablejump for x32. > > The mode is completely controled by CASE_VECTOR_MODE. > Here is the updated patch. OK for trunk? Thanks. 2011-07-18 H.J. Lu * config/i386/i386.c (ix86_print_operand): Handle 'I' to print an absolute memory reference with 64bit register. (ix86_output_addr_vec_elt): Check TARGET_LP64 instead of TARGET_64BIT for ASM_QUAD. * config/i386/i386.h (CASE_VECTOR_MODE): Check TARGET_LP64 instead of TARGET_64BIT. * config/i386/i386.md (*indirect_jump): Replace nonimmediate_operand with x32_indirect_branch_operand. (*tablejump_1): Likewise. (*call_vzeroupper): Replace call_insn_operand with x32_call_insn_operand. (*call): Likewise. (*call_rex64_ms_sysv_vzeroupper): Likewise. (*call_rex64_ms_sysv): Likewise. (*call_value_vzeroupper): Likewise. (*call_value): Likewise. (*call_value_rex64_ms_sysv_vzeroupper): Likewise. (*call_value_rex64_ms_sysv): Likewise. (*tablejump_1_x32): New. * config/i386/predicates.md (x32_indirect_branch_operand): New. (x32_call_insn_operand): Likewise. diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index c268899..bb6305a 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -13369,6 +13427,7 @@ get_some_local_dynamic_name (void) Z -- likewise, with special suffixes for x87 instructions. * -- print a star (in certain assembler syntax) A -- print an absolute memory reference. + I -- print an absolute memory reference with 64bit register. w -- print the operand as if it's a "word" (HImode) even if it isn't. s -- print a shift double count, followed by the assemblers argument delimiter. @@ -13418,6 +13477,7 @@ ix86_print_operand (FILE *file, rtx x, int code) } case 'A': + case 'I': switch (ASSEMBLER_DIALECT) { case ASM_ATT: @@ -13440,7 +13500,7 @@ ix86_print_operand (FILE *file, rtx x, int code) gcc_unreachable (); } - ix86_print_operand (file, x, 0); + ix86_print_operand (file, x, code == 'I' ? 'q' : 0); return; @@ -14862,7 +14922,7 @@ ix86_output_addr_vec_elt (FILE *file, int value) const char *directive = ASM_LONG; #ifdef ASM_QUAD - if (TARGET_64BIT) + if (TARGET_LP64) directive = ASM_QUAD; #else gcc_assert (!TARGET_64BIT); diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 4c7df9d..d3ec7e4 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -1687,7 +1687,7 @@ typedef struct ix86_args { /* Specify the machine mode that this machine uses for the index in the tablejump instruction. */ #define CASE_VECTOR_MODE \ - (!TARGET_64BIT || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode) + (!TARGET_LP64 || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode) /* Define this as 1 if `char' should by default be signed; else as 0. */ #define DEFAULT_SIGNED_CHAR 1 diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index cf0fdf4..177a687 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -10966,7 +10985,7 @@ [(set (pc) (match_operand 0 "nonimmediate_operand" ""))]) (define_insn "*indirect_jump" - [(set (pc) (match_operand:P 0 "nonimmediate_operand" "rm"))] + [(set (pc) (match_operand:P 0 "x32_indirect_branch_operand" "rm"))] "" "jmp\t%A0" [(set_attr "type" "ibr") @@ -11011,12 +11030,20 @@ }) (define_insn "*tablejump_1" - [(set (pc) (match_operand:P 0 "nonimmediate_operand" "rm")) + [(set (pc) (match_operand:P 0 "x32_indirect_branch_operand" "rm")) (use (label_ref (match_operand 1 "" "")))] "" "jmp\t%A0" [(set_attr "type" "ibr") (set_attr "length_immediate" "0")]) + +(define_insn "*tablejump_1_x32" + [(set (pc) (match_operand:SI 0 "register_operand" "r")) + (use (label_ref (match_operand 1 "" "")))] + "TARGET_X32" + "jmp\t%I0" + [(set_attr "type" "ibr") + (set_attr "length_immediate" "0")]) ;; Convert setcc + movzbl to xor + setcc if operands don't overlap. @@ -11099,7 +11126,7 @@ }) (define_insn_and_split "*call_vzeroupper" - [(call (mem:QI (match_operand:P 0 "call_insn_operand" "zm")) + [(call (mem:QI (match_operand:P 0 "x32_call_insn_operand" "zm")) (match_operand 1 "" "")) (unspec [(match_operand 2 "const_int_operand" "")] UNSPEC_CALL_NEEDS_VZEROUPPER)] @@ -11111,7 +11138,7 @@ [(set_attr "type" "call")]) (define_insn "*call" - [(call (mem:QI (match_operand:P 0 "call_insn_operand" "zm")) + [(call (mem:QI (match_operand:P 0 "x32_call_insn_operand" "zm")) (match_operand 1 "" ""))] "!SIBLING_CALL_P (insn)" "* return ix86_output_call_insn (insn, operands[0]);" @@ -11119,7 +11146,7 @@ (define_insn_and_split "*call_rex64_ms_sysv_vzeroupper" [(parallel - [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rzm")) + [(call (mem:QI (match_operand:DI 0 "x32_call_insn_operand" "rzm")) (match_operand 1 "" "")) (unspec [(const_int 0)] UNSPEC_MS_TO_SYSV_CALL) (clobber (reg:TI XMM6_REG)) @@ -11144,7 +11171,7 @@ [(set_attr "type" "call")]) (define_insn "*call_rex64_ms_sysv" - [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rzm")) + [(call (mem:QI (match_operand:DI 0 "x32_call_insn_operand" "rzm")) (match_operand 1 "" "")) (unspec [(const_int 0)] UNSPEC_MS_TO_SYSV_CALL) (clobber (reg:TI XMM6_REG)) @@ -11275,7 +11302,7 @@ (define_insn_and_split "*call_value_vzeroupper" [(set (match_operand 0 "" "") - (call (mem:QI (match_operand:P 1 "call_insn_operand" "zm")) + (call (mem:QI (match_operand:P 1 "x32_call_insn_operand" "zm")) (match_operand 2 "" ""))) (unspec [(match_operand 3 "const_int_operand" "")] UNSPEC_CALL_NEEDS_VZEROUPPER)] @@ -11288,7 +11315,7 @@ (define_insn "*call_value" [(set (match_operand 0 "" "") - (call (mem:QI (match_operand:P 1 "call_insn_operand" "zm")) + (call (mem:QI (match_operand:P 1 "x32_call_insn_operand" "zm")) (match_operand 2 "" "")))] "!SIBLING_CALL_P (insn)" "* return ix86_output_call_insn (insn, operands[1]);" @@ -11318,7 +11345,7 @@ (define_insn_and_split "*call_value_rex64_ms_sysv_vzeroupper" [(parallel [(set (match_operand 0 "" "") - (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rzm")) + (call (mem:QI (match_operand:DI 1 "x32_call_insn_operand" "rzm")) (match_operand 2 "" ""))) (unspec [(const_int 0)] UNSPEC_MS_TO_SYSV_CALL) (clobber (reg:TI XMM6_REG)) @@ -11344,7 +11371,7 @@ (define_insn "*call_value_rex64_ms_sysv" [(set (match_operand 0 "" "") - (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rzm")) + (call (mem:QI (match_operand:DI 1 "x32_call_insn_operand" "rzm")) (match_operand 2 "" ""))) (unspec [(const_int 0)] UNSPEC_MS_TO_SYSV_CALL) (clobber (reg:TI XMM6_REG)) @@ -11666,7 +11693,7 @@ (unspec:DI [(label_ref (match_operand 1 "" ""))] UNSPEC_SET_GOT_OFFSET))] - "TARGET_64BIT" + "TARGET_LP64" "movabs{q}\t{$_GLOBAL_OFFSET_TABLE_-%l1, %0|%0, OFFSET FLAT:_GLOBAL_OFFSET_TABLE_-%l1}" [(set_attr "type" "imov") (set_attr "length_immediate" "0") diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md index 2c75147..4e61ce4 100644 --- a/gcc/config/i386/predicates.md +++ b/gcc/config/i386/predicates.md @@ -1181,3 +1191,12 @@ return false; return true; }) + +;; Return nonzero if OP is indirect branch target representable on x32. +(define_predicate "x32_indirect_branch_operand" + (if_then_else (match_test "TARGET_X32") + (match_operand 0 "register_operand") + (match_operand 0 "nonimmediate_operand"))) + +;; Test for a valid operand for a call instruction on x32 +(define_predicate "x32_call_insn_operand" + (if_then_else (match_test "TARGET_X32") + (ior (match_operand 0 "constant_call_address_operand") + (match_operand 0 "call_register_no_elim_operand")) + (match_operand 0 "call_insn_operand")))