From patchwork Tue Jul 13 16:35:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 1504737 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=Yd24gPOA; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GPR9T3Ltgz9sXN for ; Wed, 14 Jul 2021 02:36:44 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A1DC2396E473 for ; Tue, 13 Jul 2021 16:36:41 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A1DC2396E473 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1626194201; bh=mtl7MamY060XWEm1mklr0rDek/AmBsa/Q5IUyd/xvRQ=; h=References:In-Reply-To:Date:Subject:To:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=Yd24gPOAWgsxQ2Lb9FpG+fihXHzkT6Gkr37/2fXywz4h6Isxqnk4fXSa5ZnniYEZa TJI6Vfrhzp4h2dfXvBJ2PH38xvF8pqBkGfYHM3ASoFe01Opc7r+XUSQRhOx05seQA/ 3o9QfO3Cew+Rcwst6wuQ95xiafO0bY4p2TOwePZ8= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pf1-x436.google.com (mail-pf1-x436.google.com [IPv6:2607:f8b0:4864:20::436]) by sourceware.org (Postfix) with ESMTPS id E6012388A80D for ; Tue, 13 Jul 2021 16:35:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org E6012388A80D Received: by mail-pf1-x436.google.com with SMTP id a127so20148931pfa.10 for ; Tue, 13 Jul 2021 09:35:55 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=mtl7MamY060XWEm1mklr0rDek/AmBsa/Q5IUyd/xvRQ=; b=k40FsuCQZiKr5o5mEnIrlzQ2CV3CTw+iCMPinzlajL0pKY+qeVAnTJB8i13gzngtOL mVpzKfHlThBB7DOWPad6ksuQVrb6u63tCxi7CCZ53bhqGVHP4QaZl+IfgeFZsASOM9QJ acgA7gXtRPz2GtJ48/FMGS8DRLS8qvABuX+0N7grNYNPzhSjBEJ2lFxAz46H2nWVtS7u Bz2MPpqdiISjqgNNc9AQG82SYPY4AVFrpqk/9Xdp2pn7mH3uSTEnLHFQRWG++IGH6uRw BnttNRZpADMHFyzu4U30UI48PkqatEi6WxcvHKqjnfKUdzmHpAmmzgWz1KNZKHtto/z0 a17A== X-Gm-Message-State: AOAM530t6zPZDmK0N3l945VdAzvSARfTP5p4JoWk3dJJhzsqIBH+njWL AhK9ptAWWD/UW/q3fKSWvvZt9qZqmFkeE97Bo5M= X-Google-Smtp-Source: ABdhPJxEFwdGFmsTci3mpVxj/9at8+P87p3GdKVfhY9KcUjXNsWHpy15WMWDZf+IkcI5nLGb70QofxKchRGX8T7mMWo= X-Received: by 2002:aa7:8812:0:b029:32d:8252:fd0 with SMTP id c18-20020aa788120000b029032d82520fd0mr5433488pfo.48.1626194154858; Tue, 13 Jul 2021 09:35:54 -0700 (PDT) MIME-Version: 1.0 References: <20210713015130.6297-1-hjl.tools@gmail.com> <20210713065556.GI2380545@tucnak> In-Reply-To: <20210713065556.GI2380545@tucnak> Date: Tue, 13 Jul 2021 09:35:18 -0700 Message-ID: Subject: [PATCH v3] x86: Don't enable UINTR in 32-bit mode To: Jakub Jelinek , Hongyu Wang X-Spam-Status: No, score=-3031.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "H.J. Lu via Gcc-patches" From: "H.J. Lu" Reply-To: "H.J. Lu" Cc: GCC Patches Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" On Mon, Jul 12, 2021 at 11:56 PM Jakub Jelinek wrote: > > On Mon, Jul 12, 2021 at 06:51:30PM -0700, H.J. Lu wrote: > > @@ -404,9 +404,18 @@ const char *host_detect_local_cpu (int argc, const char **argv) > > if (argc < 1) > > return NULL; > > I think it would be simpler to use 2 arguments instead of one. > So change the above to if (argc < 2) Fixed. > > > > - arch = !strcmp (argv[0], "arch"); > > + arch = !strncmp (argv[0], "arch", 4); > > > > - if (!arch && strcmp (argv[0], "tune")) > > + if (!arch && strncmp (argv[0], "tune", 4)) > > + return NULL; > > Keep strcmp as is here. Fixed. > > + > > + bool codegen_x86_64; > > + > > + if (!strcmp (argv[0] + 4, "32")) > > + codegen_x86_64 = false; > > + else if (!strcmp (argv[0] + 4, "64")) > > + codegen_x86_64 = true; > > + else > > return NULL; > > Check argv[1] here instead. Fixed. > > @@ -813,7 +826,8 @@ const char *host_detect_local_cpu (int argc, const char **argv) > > } > > > > done: > > - return concat (cache, "-m", argv[0], "=", cpu, options, NULL); > > + const char *moption = arch ? "-march=" : "-mtune="; > > + return concat (cache, moption, cpu, options, NULL); > > } > > #else > > You don't need this change. Fixed. > > diff --git a/gcc/config/i386/i386-options.c b/gcc/config/i386/i386-options.c > > index 7a35c468da3..7cba655595e 100644 > > --- a/gcc/config/i386/i386-options.c > > +++ b/gcc/config/i386/i386-options.c > > @@ -2109,6 +2109,7 @@ ix86_option_override_internal (bool main_args_p, > > #define DEF_PTA(NAME) \ > > if (((processor_alias_table[i].flags & PTA_ ## NAME) != 0) \ > > && PTA_ ## NAME != PTA_64BIT \ > > + && (TARGET_64BIT || PTA_ ## NAME != PTA_UINTR) \ > > && !TARGET_EXPLICIT_ ## NAME ## _P (opts)) \ > > SET_TARGET_ ## NAME (opts); > > #include "i386-isa.def" > > diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h > > index 8c3eace56da..ae9f455c48d 100644 > > --- a/gcc/config/i386/i386.h > > +++ b/gcc/config/i386/i386.h > > @@ -577,9 +577,12 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); > > #define CC1_CPU_SPEC CC1_CPU_SPEC_1 > > #else > > #define CC1_CPU_SPEC CC1_CPU_SPEC_1 \ > > -"%{march=native:%>march=native %:local_cpu_detect(arch) \ > > - %{!mtune=*:%>mtune=native %:local_cpu_detect(tune)}} \ > > -%{mtune=native:%>mtune=native %:local_cpu_detect(tune)}" > > +"%{" OPT_ARCH32 ":%{march=native:%>march=native %:local_cpu_detect(arch32) \ > > + %{!mtune=*:%>mtune=native %:local_cpu_detect(tune32)}}}" \ > > +"%{" OPT_ARCH32 ":%{mtune=native:%>mtune=native %:local_cpu_detect(tune32)}}" \ > > +"%{" OPT_ARCH64 ":%{march=native:%>march=native %:local_cpu_detect(arch64) \ > > + %{!mtune=*:%>mtune=native %:local_cpu_detect(tune64)}}}" \ > > +"%{" OPT_ARCH64 ":%{mtune=native:%>mtune=native %:local_cpu_detect(tune64)}}" > > And you can use > #define ARCH_ARG "%{" OPT_ARCH64 ":64;32}" I added #define ARCH_ARG "%{" OPT_ARCH64 ":64;:32}" > %:local_cpu_detect(arch, " ARCH_ARG ") > etc. > > Jakub > Here is the v3 patch. OK for master? Thanks. From ceab81ef97ab102c410830c41ba7fea911170d1a Mon Sep 17 00:00:00 2001 From: "H.J. Lu" Date: Fri, 9 Jul 2021 09:16:01 -0700 Subject: [PATCH v3] x86: Don't enable UINTR in 32-bit mode UINTR is available only in 64-bit mode. Since the codegen target is unknown when the the gcc driver is processing -march=native, to properly handle UINTR for -march=native: 1. Pass "arch [32|64]" and "tune [32|64]" to host_detect_local_cpu to indicate 32-bit and 64-bit codegen. 2. Change ix86_option_override_internal to enable UINTR only in 64-bit mode for -march=CPU when PTA_CPU includes PTA_UINTR. gcc/ PR target/101395 * config/i386/driver-i386.c (host_detect_local_cpu): Check "arch [32|64]" and "tune [32|64]" for 32-bit and 64-bit codegen. Enable UINTR only for 64-bit codegen. * config/i386/i386-options.c (ix86_option_override_internal::DEF_PTA): Skip PTA_UINTR if not in 64-bit mode. * config/i386/i386.h (ARCH_ARG): New. (CC1_CPU_SPEC): Pass "[arch|tune] 32" for 32-bit codegen and "[arch|tune] 64" for 64-bit codegen. gcc/testsuite/ PR target/101395 * gcc.target/i386/pr101395-1.c: New test. * gcc.target/i386/pr101395-2.c: Likewise. * gcc.target/i386/pr101395-3.c: Likewise. --- gcc/config/i386/driver-i386.c | 25 ++++++++++++++++------ gcc/config/i386/i386-options.c | 1 + gcc/config/i386/i386.h | 7 +++--- gcc/testsuite/gcc.target/i386/pr101395-1.c | 12 +++++++++++ gcc/testsuite/gcc.target/i386/pr101395-2.c | 22 +++++++++++++++++++ gcc/testsuite/gcc.target/i386/pr101395-3.c | 6 ++++++ 6 files changed, 64 insertions(+), 9 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr101395-1.c create mode 100644 gcc/testsuite/gcc.target/i386/pr101395-2.c create mode 100644 gcc/testsuite/gcc.target/i386/pr101395-3.c diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c index dd9236616b4..f844a168ddb 100644 --- a/gcc/config/i386/driver-i386.c +++ b/gcc/config/i386/driver-i386.c @@ -370,9 +370,9 @@ detect_caches_intel (bool xeon_mp, unsigned max_level, } /* This will be called by the spec parser in gcc.c when it sees - a %:local_cpu_detect(args) construct. Currently it will be called - with either "arch" or "tune" as argument depending on if -march=native - or -mtune=native is to be substituted. + a %:local_cpu_detect(args) construct. Currently it will be + called with either "arch [32|64]" or "tune [32|64]" as argument + depending on if -march=native or -mtune=native is to be substituted. It returns a string containing new command line parameters to be put at the place of the above two options, depending on what CPU @@ -401,7 +401,7 @@ const char *host_detect_local_cpu (int argc, const char **argv) unsigned int l2sizekb = 0; - if (argc < 1) + if (argc < 2) return NULL; arch = !strcmp (argv[0], "arch"); @@ -409,6 +409,15 @@ const char *host_detect_local_cpu (int argc, const char **argv) if (!arch && strcmp (argv[0], "tune")) return NULL; + bool codegen_x86_64; + + if (!strcmp (argv[1], "32")) + codegen_x86_64 = false; + else if (!strcmp (argv[1], "64")) + codegen_x86_64 = true; + else + return NULL; + struct __processor_model cpu_model = { }; struct __processor_model2 cpu_model2 = { }; unsigned int cpu_features2[SIZE_OF_CPU_FEATURES] = { }; @@ -804,8 +813,12 @@ const char *host_detect_local_cpu (int argc, const char **argv) if (isa_names_table[i].option) { if (has_feature (isa_names_table[i].feature)) - options = concat (options, " ", - isa_names_table[i].option, NULL); + { + if (codegen_x86_64 + || isa_names_table[i].feature != FEATURE_UINTR) + options = concat (options, " ", + isa_names_table[i].option, NULL); + } else options = concat (options, neg_option, isa_names_table[i].option + 2, NULL); diff --git a/gcc/config/i386/i386-options.c b/gcc/config/i386/i386-options.c index 7a35c468da3..7cba655595e 100644 --- a/gcc/config/i386/i386-options.c +++ b/gcc/config/i386/i386-options.c @@ -2109,6 +2109,7 @@ ix86_option_override_internal (bool main_args_p, #define DEF_PTA(NAME) \ if (((processor_alias_table[i].flags & PTA_ ## NAME) != 0) \ && PTA_ ## NAME != PTA_64BIT \ + && (TARGET_64BIT || PTA_ ## NAME != PTA_UINTR) \ && !TARGET_EXPLICIT_ ## NAME ## _P (opts)) \ SET_TARGET_ ## NAME (opts); #include "i386-isa.def" diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 8c3eace56da..324e8a952d9 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -576,10 +576,11 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); #ifndef HAVE_LOCAL_CPU_DETECT #define CC1_CPU_SPEC CC1_CPU_SPEC_1 #else +#define ARCH_ARG "%{" OPT_ARCH64 ":64;:32}" #define CC1_CPU_SPEC CC1_CPU_SPEC_1 \ -"%{march=native:%>march=native %:local_cpu_detect(arch) \ - %{!mtune=*:%>mtune=native %:local_cpu_detect(tune)}} \ -%{mtune=native:%>mtune=native %:local_cpu_detect(tune)}" +"%{march=native:%>march=native %:local_cpu_detect(arch " ARCH_ARG ") \ + %{!mtune=*:%>mtune=native %:local_cpu_detect(tune " ARCH_ARG ")}} \ +%{mtune=native:%>mtune=native %:local_cpu_detect(tune " ARCH_ARG ")}" #endif #endif diff --git a/gcc/testsuite/gcc.target/i386/pr101395-1.c b/gcc/testsuite/gcc.target/i386/pr101395-1.c new file mode 100644 index 00000000000..74c8bfe891a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr101395-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=sapphirerapids" } */ + +#ifdef __x86_64__ +# ifndef __UINTR__ +# error UINTR is not enabled for Sapphirerapids +# endif +#else +# ifdef __UINTR__ +# error UINTR is not usable in 32-bit mode +# endif +#endif diff --git a/gcc/testsuite/gcc.target/i386/pr101395-2.c b/gcc/testsuite/gcc.target/i386/pr101395-2.c new file mode 100644 index 00000000000..f2b677f8c80 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr101395-2.c @@ -0,0 +1,22 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -march=native" } */ + +int +main () +{ + if (__builtin_cpu_supports ("uintr")) + { +#ifdef __x86_64__ +# ifndef __UINTR__ + __builtin_abort (); +# endif +#else +# ifdef __UINTR__ + __builtin_abort (); +# endif +#endif + return 0; + } + + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/pr101395-3.c b/gcc/testsuite/gcc.target/i386/pr101395-3.c new file mode 100644 index 00000000000..bc6ab423c93 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr101395-3.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=native -mno-uintr" } */ + +#ifdef __UINTR__ +# error UINTR should be disabled +#endif -- 2.31.1