From patchwork Mon Aug 9 19:14:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 1515172 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=QSSS5+50; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Gk5QS6RSSz9sRK for ; Tue, 10 Aug 2021 05:15:43 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id F01F638A8860 for ; Mon, 9 Aug 2021 19:15:40 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org F01F638A8860 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1628536541; bh=RBut9a4WYJv9lvCnC5RrVOCN77v36eKWEOiWZkyCato=; h=References:In-Reply-To:Date:Subject:To:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=QSSS5+50Nc7M1Dhr92PHPSpASIB4fihTKZXs/o2inDv2+yBEQtWH74nd1Euq897ZM 7M9OTE5LwOkLAOUtrhR0pIuYJmvWnxal3i9al53QUpXlPRd4SmMH7KT0KU+JjORphA kqSzvKiK6D9f1czyFzc9jVqSqDO/9Fs+WuNn7+qw= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pl1-x631.google.com (mail-pl1-x631.google.com [IPv6:2607:f8b0:4864:20::631]) by sourceware.org (Postfix) with ESMTPS id AFAF9385800E for ; Mon, 9 Aug 2021 19:15:09 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org AFAF9385800E Received: by mail-pl1-x631.google.com with SMTP id c16so17603361plh.7 for ; Mon, 09 Aug 2021 12:15:09 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=RBut9a4WYJv9lvCnC5RrVOCN77v36eKWEOiWZkyCato=; b=A3yh82pVEaqaQYpVhveqVRXui0QKUKU2WGUuSVyRbwlq/0Yn58oJIhjQJk5J6sLctH Mfd/R+wns6nD0ufTjlwnQ7/mrBoadZHck1kYRi22bTvX+lBZ6kyo+DXNtWH7rMqzaXf7 DO6MqUwl4cMMpi4aPSFL3+vLtTByA+PrOUI40rVQO0KfP6COiuZLHzAEBYfhsqYVh2Mh kBH5lSQqrm/qrHuKwDkeJCxJ9/5bVSyc6IKB9HX66vWvQ3ZUyn9Tfbmo3zTy9E4nmmyA trajDM6EnXNAgaU0dxIXVZDpQnMCs5UWnSdfDWzvwRdVJ/yYaj9uFLRv7hXh7qdlc09W tvtQ== X-Gm-Message-State: AOAM533FJbrU0juHEeDLz3N3JgR4KoHuIA7xf8xeLDTpUprDTLsc2GJv YHmC/RJTuHI7Pf3WvDGZEKIvG09Y32s9kNpRJT4= X-Google-Smtp-Source: ABdhPJzV1qBCwOzBTvrKmBH5iakIaY91P5WbyUdxCuLevS2/QrOoy5VZ9UBRmE/1mC/jJTJxXwOEJIFkryWIOnBnruk= X-Received: by 2002:aa7:946a:0:b029:3c8:74bc:dcda with SMTP id t10-20020aa7946a0000b02903c874bcdcdamr16369168pfq.57.1628536508791; Mon, 09 Aug 2021 12:15:08 -0700 (PDT) MIME-Version: 1.0 References: <20210807144132.3645400-1-hjl.tools@gmail.com> In-Reply-To: Date: Mon, 9 Aug 2021 12:14:32 -0700 Message-ID: Subject: [PATCH v4] x86: Optimize load of const FP all bits set vectors To: Uros Bizjak X-Spam-Status: No, score=-3030.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "H.J. Lu via Gcc-patches" From: "H.J. Lu" Reply-To: "H.J. Lu" Cc: liuhongt , "gcc-patches@gcc.gnu.org" Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" On Mon, Aug 9, 2021 at 11:53 AM Uros Bizjak wrote: > > On Mon, Aug 9, 2021 at 7:47 PM H.J. Lu wrote: > > > > On Mon, Aug 9, 2021 at 8:27 AM Uros Bizjak wrote: > > > > > > On Mon, Aug 9, 2021 at 5:24 PM H.J. Lu wrote: > > > > > > > > On Sun, Aug 8, 2021 at 1:23 PM Uros Bizjak wrote: > > > > > > > > > > On Sat, Aug 7, 2021 at 4:41 PM H.J. Lu wrote: > > > > > > > > > > > > Update vector_all_ones_operand to return true for const all 1s float > > > > > > vectors. > > > > > > > > > > > > gcc/ > > > > > > > > > > > > PR target/101804 > > > > > > * config/i386/predicates.md (vector_all_ones_operand): Return > > > > > > true for const all 1s float vectors. > > > > > > > > > > > > gcc/testsuite/ > > > > > > > > > > > > PR target/101804 > > > > > > * gcc.target/i386/avx2-gather-2.c: Pass -march=skylake instead > > > > > > of "-mavx2 -mtune=skylake". Scan vpcmpeqd. > > > > > > > > > > No, vector_all_ones_operand is intended to be integer minus-one. Use > > > > > float_vector_all_ones_operand in a specific place, where it is needed. > > > > > > > > > > > > > Like this? > > > > > > Please also add a new constraint, BC is intended for integer values. > > > > > > Uros. > > > > Here is the v3 patch with the new BF constraint. OK for master? > > OK with some comment fixes. > > +;; C Integer SSE constant -1 operand. > +;; F Floating-point SSE constant -1 operand. > > Maybe we should simply say "... SSE constant with all bits set" here. > "... SSE constant -1" is ambiguous, someone can interpret this as a > constant -1.0. > > - "@internal SSE constant -1 operand." > + "@internal integer SSE constant -1 operand." > > Also here. > > +(define_constraint "BF" > + "@internal floating-point SSE constant -1 operand." > > And here. > > Thanks, > Uros. This is the patch I am going to check in. Thanks. From 93499102a52d29974b47e1d32274f6a08a4d6580 Mon Sep 17 00:00:00 2001 From: "H.J. Lu" Date: Fri, 6 Aug 2021 12:32:01 -0700 Subject: [PATCH v4] x86: Optimize load of const FP all bits set vectors Check float_vector_all_ones_operand for vector floating-point modes to optimize load of const floating-point all bits set vectors. gcc/ PR target/101804 * config/i386/constraints.md (BC): Document for integer SSE constant all bits set operand. (BF): New constraint for const floating-point all bits set vectors. * config/i386/i386.c (standard_sse_constant_p): Likewise. (standard_sse_constant_opcode): Likewise. * config/i386/sse.md (sseconstm1): New mode attribute. (mov_internal): Replace BC with . gcc/testsuite/ PR target/101804 * gcc.target/i386/avx2-gather-2.c: Pass -march=skylake instead of "-mavx2 -mtune=skylake". Scan vpcmpeqd. Fix --- gcc/config/i386/constraints.md | 10 ++++++++-- gcc/config/i386/i386.c | 11 +++++++++-- gcc/config/i386/sse.md | 11 ++++++++++- gcc/testsuite/gcc.target/i386/avx2-gather-2.c | 3 ++- 4 files changed, 29 insertions(+), 6 deletions(-) diff --git a/gcc/config/i386/constraints.md b/gcc/config/i386/constraints.md index 4aa28a5621c..87cceac4cfb 100644 --- a/gcc/config/i386/constraints.md +++ b/gcc/config/i386/constraints.md @@ -166,7 +166,8 @@ (define_register_constraint "YW" ;; s Sibcall memory operand, not valid for TARGET_X32 ;; w Call memory operand, not valid for TARGET_X32 ;; z Constant call address operand. -;; C SSE constant operand. +;; C Integer SSE constant with all bits set operand. +;; F Floating-point SSE constant with all bits set operand. (define_constraint "Bf" "@internal Flags register operand." @@ -216,11 +217,16 @@ (define_constraint "Bz" (match_operand 0 "constant_call_address_operand")) (define_constraint "BC" - "@internal SSE constant -1 operand." + "@internal integer SSE constant with all bits set operand." (and (match_test "TARGET_SSE") (ior (match_test "op == constm1_rtx") (match_operand 0 "vector_all_ones_operand")))) +(define_constraint "BF" + "@internal floating-point SSE constant with all bits set operand." + (and (match_test "TARGET_SSE") + (match_operand 0 "float_vector_all_ones_operand"))) + ;; Integer constant constraints. (define_constraint "Wb" "Integer constant in the range 0 @dots{} 7, for 8-bit shifts." diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index aea224ab235..4d4ab6a03d6 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -5073,7 +5073,11 @@ standard_sse_constant_p (rtx x, machine_mode pred_mode) if (x == const0_rtx || const0_operand (x, mode)) return 1; - if (x == constm1_rtx || vector_all_ones_operand (x, mode)) + if (x == constm1_rtx + || vector_all_ones_operand (x, mode) + || ((GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT + || GET_MODE_CLASS (pred_mode) == MODE_VECTOR_FLOAT) + && float_vector_all_ones_operand (x, mode))) { /* VOIDmode integer constant, get mode from the predicate. */ if (mode == VOIDmode) @@ -5171,7 +5175,10 @@ standard_sse_constant_opcode (rtx_insn *insn, rtx *operands) gcc_unreachable (); } } - else if (x == constm1_rtx || vector_all_ones_operand (x, mode)) + else if (x == constm1_rtx + || vector_all_ones_operand (x, mode) + || (GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT + && float_vector_all_ones_operand (x, mode))) { enum attr_mode insn_mode = get_attr_mode (insn); diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index a46a2373547..5255d42900e 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -777,6 +777,15 @@ (define_mode_attr sseinsnmode (V4SF "V4SF") (V2DF "V2DF") (TI "TI")]) +;; SSE constant -1 constraint +(define_mode_attr sseconstm1 + [(V64QI "BC") (V32HI "BC") (V16SI "BC") (V8DI "BC") (V4TI "BC") + (V32QI "BC") (V16HI "BC") (V8SI "BC") (V4DI "BC") (V2TI "BC") + (V16QI "BC") (V8HI "BC") (V4SI "BC") (V2DI "BC") (V1TI "BC") + (V16SF "BF") (V8DF "BF") + (V8SF "BF") (V4DF "BF") + (V4SF "BF") (V2DF "BF")]) + ;; Mapping of vector modes to corresponding mask size (define_mode_attr avx512fmaskmode [(V64QI "DI") (V32QI "SI") (V16QI "HI") @@ -1056,7 +1065,7 @@ (define_insn "mov_internal" [(set (match_operand:VMOVE 0 "nonimmediate_operand" "=v,v ,v ,m") (match_operand:VMOVE 1 "nonimmediate_or_sse_const_operand" - " C,BC,vm,v"))] + " C,,vm,v"))] "TARGET_SSE && (register_operand (operands[0], mode) || register_operand (operands[1], mode))" diff --git a/gcc/testsuite/gcc.target/i386/avx2-gather-2.c b/gcc/testsuite/gcc.target/i386/avx2-gather-2.c index 1a704afd834..ad5ef73107c 100644 --- a/gcc/testsuite/gcc.target/i386/avx2-gather-2.c +++ b/gcc/testsuite/gcc.target/i386/avx2-gather-2.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ -/* { dg-options "-O3 -mavx2 -fdump-tree-vect-details -mtune=skylake" } */ +/* { dg-options "-O3 -fdump-tree-vect-details -march=skylake" } */ #include "avx2-gather-1.c" /* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 16 "vect" } } */ +/* { dg-final { scan-assembler "vpcmpeqd" } } */ -- 2.31.1