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[3/4,PR,target/88808] Enable bitwise operator for AVX512 masks.

Message ID CAMZc-bzvFn+VdNk9jqv-p-s=5cQ3eysgYTzMyiX3tO8U8x=MFg@mail.gmail.com
State New
Headers show
Series [1/4,PR,target/88808] Enable bitwise operator for AVX512 masks. | expand

Commit Message

Hongtao Liu Aug. 14, 2020, 8:26 a.m. UTC 
1. Set cost of movement inside mask registers a bit higher than gpr's.
2. Set cost of movement between mask register and gpr much higher than movement
   inside gpr, but still less equal than load/store.
3. Set cost of mask register load/store a bit higher than gpr load/store.

Comments

Uros Bizjak Aug. 17, 2020, 9:37 a.m. UTC | #1 
On Fri, Aug 14, 2020 at 10:25 AM Hongtao Liu <crazylht@gmail.com> wrote:
>
> 1. Set cost of movement inside mask registers a bit higher than gpr's.
> 2. Set cost of movement between mask register and gpr much higher than movement
>    inside gpr, but still less equal than load/store.
> 3. Set cost of mask register load/store a bit higher than gpr load/store.

I have no comment here (fine tuning costs is a painful task ;) )

Uros.
diff mbox series

Patch

From 5342006fea6b9f2b863590b400e73340c5dff21a Mon Sep 17 00:00:00 2001
From: liuhongt <hongtao.liu@intel.com>
Date: Thu, 24 Oct 2019 11:13:00 +0800
Subject: [PATCH 3/4] According to instruction_tables.pdf

1. Set cost of movement inside mask registers a bit higher than gpr's.
2. Set cost of movement between mask register and gpr much higher than movement
   inside gpr, but still less equal than load/store.
3. Set cost of mask register load/store a bit higher than gpr load/store.
---
 gcc/config/i386/x86-tune-costs.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/gcc/config/i386/x86-tune-costs.h b/gcc/config/i386/x86-tune-costs.h
index 256c84e364e..a782a9dd9e3 100644
--- a/gcc/config/i386/x86-tune-costs.h
+++ b/gcc/config/i386/x86-tune-costs.h
@@ -1727,12 +1727,12 @@  struct processor_costs skylake_cost = {
   {8, 8, 8, 12, 24},			/* cost of storing SSE registers
 					   in 32,64,128,256 and 512-bit */
   6, 6,					/* SSE->integer and integer->SSE moves */
-  2, 2,				/* mask->integer and integer->mask moves */
-  {4, 4, 4},				/* cost of loading mask register
+  4, 6,				/* mask->integer and integer->mask moves */
+  {6, 6, 6},				/* cost of loading mask register
 					   in QImode, HImode, SImode.  */
-  {6, 6, 6},				/* cost if storing mask register
+  {8, 8, 8},				/* cost if storing mask register
 					   in QImode, HImode, SImode.  */
-  2,					/* cost of moving mask register.  */
+  3,					/* cost of moving mask register.  */
   /* End of register allocator costs.  */
   },
 
-- 
2.18.1