From patchwork Wed Nov 7 09:14:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Hua X-Patchwork-Id: 994152 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-489218-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="a+aZ9LvN"; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="mGSRiJS5"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42qgkt2ZfKz9sCX for ; Wed, 7 Nov 2018 20:16:06 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:references:in-reply-to:from:date:message-id :subject:to:cc:content-type; q=dns; s=default; b=uKfYJTBMiCom3/Q bcHV9efZFm5FMeWOEK3J7tBFc6Jq7i2ZpzagNfiGKWlrJ61FVRSPZJCpaQZ0hD/v BHX3ErhPt+c4g+CxGEfS+Z3v/hhHpE7Q+iy9wjEH30Ixxx+5IhEk/OqfygNMqT6f XMR3gXn/xjfZClgJYBB0QAsRNprc= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:references:in-reply-to:from:date:message-id :subject:to:cc:content-type; s=default; bh=ux8wsqEyakEyw+uQcshTR t8hG4E=; b=a+aZ9LvNc2u1EZ8RJvgJDrhz5uqfLyu1+roF+j6+3aA3HApC0W3GR oCX2FKvSnnuEOID0uC1TAbdenpX6YkhBUzXIaL/geYaeR6G3qFyM25mwsCgw+gjr u+wrcD1Z6ejWxoO+7rq+zCL09kyQ/t5ybwHnRuJueXE6D5Dwt9noZ4= Received: (qmail 30495 invoked by alias); 7 Nov 2018 09:15:57 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 30242 invoked by uid 89); 7 Nov 2018 09:15:40 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS, TIME_LIMIT_EXCEEDED autolearn=unavailable version=3.3.2 spammy=t0 X-HELO: mail-ot1-f44.google.com Received: from mail-ot1-f44.google.com (HELO mail-ot1-f44.google.com) (209.85.210.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 07 Nov 2018 09:15:22 +0000 Received: by mail-ot1-f44.google.com with SMTP id z33so14035857otz.11 for ; Wed, 07 Nov 2018 01:15:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=/jTxF9jIJjnPhmPdmScuuJiB+0IW9QJHoPUpxetMC+8=; b=mGSRiJS5nDcNJAp/oSyxIAnlf+bQ+PbGKkFL0nFBfp0i+rjBifDtlCffsmf+/Z2Q/4 2w9LZbB5oDJ9aM9TcytolGUxHDLFaob55clSv/8OShm0Bq+NmrtqCHJOYEXsU2vdblM9 bPYPQroSh2My5xH53P0BCqDHttTgDnYW9YK9xkRtZHQ1rxOvNCe5GjRDkkH4IHqAbwBf WszCBqog5sCOqAJQJzOFtR8Ly297E7JS5ho4/ZTYQ7JXdSgPKQxiS7fu2oi3QZ68xg2U R3crgHlqR+BExmM67hyWdlSeYqFOKaawoeg/At6gRndDr0jg0Zb6PWhSs0FKI8vQ8eRs 47vQ== MIME-Version: 1.0 References: In-Reply-To: From: Paul Hua Date: Wed, 7 Nov 2018 17:14:53 +0800 Message-ID: Subject: [PATCH v4 3/6, Committed] [MIPS] Add Loongson EXTensions R2 (EXT2) instructions support To: gcc-patches Cc: Matthew Fortune X-IsSubscribed: yes On Tue, Oct 16, 2018 at 10:50 AM Paul Hua wrote: > > From 73a4aac5034307cf7369bb70fa407709502fffbf Mon Sep 17 00:00:00 2001 From: Chenghua Xu Date: Fri, 31 Aug 2018 11:55:48 +0800 Subject: [PATCH 3/6] Add support for Loongson EXT2 instructions. gcc/ * config/mips/mips-protos.h (mips_loongson_ext2_prefetch_cookie): New prototype. * config/mips/mips.c (mips_loongson_ext2_prefetch_cookie): New. (mips_option_override): Enable TARGET_LOONGSON_EXT when TARGET_LOONGSON_EXT2 is true. * config/mips/mips.h (TARGET_CPU_CPP_BUILTINS): Define __mips_loongson_ext2, __mips_loongson_ext_rev=2. (ISA_HAS_CTZ_CTO): New, true if TARGET_LOONGSON_EXT2. (ISA_HAS_PREFETCH): Include TARGET_LOONGSON_EXT and TARGET_LOONGSON_EXT2. (ASM_SPEC): Add mloongson-ext2 and mno-loongson-ext2. (define_insn "ctz2"): New insn pattern. (define_insn "prefetch"): Include TARGET_LOONGSON_EXT2. (define_insn "prefetch_indexed_"): Include TARGET_LOONGSON_EXT and TARGET_LOONGSON_EXT2. * config/mips/mips.opt (-mloongson-ext2): Add option. * gcc/doc/invoke.texi (-mloongson-ext2): Document. gcc/testsuite/ * gcc.target/mips/loongson-ctz.c: New test. * gcc.target/mips/loongson-dctz.c: Likewise. * gcc.target/mips/mips.exp (mips_option_groups): Add -mloongson-ext2 option. --- gcc/config/mips/mips-protos.h | 1 + gcc/config/mips/mips.c | 28 +++++++++++ gcc/config/mips/mips.h | 15 +++++- gcc/config/mips/mips.md | 47 +++++++++++++++++-- gcc/config/mips/mips.opt | 4 ++ gcc/doc/invoke.texi | 7 +++ gcc/testsuite/gcc.target/mips/loongson-ctz.c | 11 +++++ gcc/testsuite/gcc.target/mips/loongson-dctz.c | 11 +++++ gcc/testsuite/gcc.target/mips/mips.exp | 1 + 9 files changed, 120 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/mips/loongson-ctz.c create mode 100644 gcc/testsuite/gcc.target/mips/loongson-dctz.c diff --git a/gcc/config/mips/mips-protos.h b/gcc/config/mips/mips-protos.h index 099120db7b4..7cde2424016 100644 --- a/gcc/config/mips/mips-protos.h +++ b/gcc/config/mips/mips-protos.h @@ -323,6 +323,7 @@ extern bool mips_linked_madd_p (rtx_insn *, rtx_insn *); extern bool mips_store_data_bypass_p (rtx_insn *, rtx_insn *); extern int mips_dspalu_bypass_p (rtx, rtx); extern rtx mips_prefetch_cookie (rtx, rtx); +extern rtx mips_loongson_ext2_prefetch_cookie (rtx, rtx); extern const char *current_section_name (void); extern unsigned int current_section_flags (void); diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index b579c3c3a2a..1c2075044d0 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -15142,6 +15142,22 @@ mips_prefetch_cookie (rtx write, rtx locality) /* store_retained / load_retained. */ return GEN_INT (INTVAL (write) + 6); } + +/* Loongson EXT2 only implements perf hint=0 (prefetch for load) and hint=1 + (prefetch for store), other hint just scale to hint = 0 and hint = 1. */ + +rtx +mips_loongson_ext2_prefetch_cookie (rtx write, rtx locality) +{ + /* store. */ + if (INTVAL (write) == 1) + return GEN_INT (INTVAL (write)); + + /* load. */ + if (INTVAL (write) == 0) + return GEN_INT (INTVAL (write)); +} + /* Flags that indicate when a built-in function is available. @@ -20171,6 +20187,18 @@ mips_option_override (void) if (TARGET_LOONGSON_MMI && !TARGET_HARD_FLOAT_ABI) error ("%<-mloongson-mmi%> must be used with %<-mhard-float%>"); + /* If TARGET_LOONGSON_EXT2, enable TARGET_LOONGSON_EXT. */ + if (TARGET_LOONGSON_EXT2) + { + /* Make sure that when TARGET_LOONGSON_EXT2 is true, TARGET_LOONGSON_EXT + is true. If a user explicitly says -mloongson-ext2 -mno-loongson-ext + then that is an error. */ + if (!TARGET_LOONGSON_EXT + && !((target_flags_explicit & MASK_LOONGSON_EXT) == 0)) + error ("%<-mloongson-ext2%> must be used with %<-mloongson-ext%>"); + target_flags |= MASK_LOONGSON_EXT; + } + /* .eh_frame addresses should be the same width as a C pointer. Most MIPS ABIs support only one pointer size, so the assembler will usually know exactly how big an .eh_frame address is. diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 7237c8da8ac..beeb4bcf20d 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -600,6 +600,13 @@ struct mips_cpu_info { if (TARGET_LOONGSON_EXT) \ { \ builtin_define ("__mips_loongson_ext"); \ + if (TARGET_LOONGSON_EXT2) \ + { \ + builtin_define ("__mips_loongson_ext2"); \ + builtin_define ("__mips_loongson_ext_rev=2"); \ + } \ + else \ + builtin_define ("__mips_loongson_ext_rev=1"); \ } \ \ /* Historical Octeon macro. */ \ @@ -1134,6 +1141,9 @@ struct mips_cpu_info { /* ISA has count leading zeroes/ones instruction (not implemented). */ #define ISA_HAS_CLZ_CLO (mips_isa_rev >= 1 && !TARGET_MIPS16) +/* ISA has count tailing zeroes/ones instruction. */ +#define ISA_HAS_CTZ_CTO (TARGET_LOONGSON_EXT2) + /* ISA has three operand multiply instructions that put the high part in an accumulator: mulhi or mulhiu. */ #define ISA_HAS_MULHI ((TARGET_MIPS5400 \ @@ -1195,7 +1205,9 @@ struct mips_cpu_info { 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT. (prefx is a cop1x instruction, so can only be used if FP is enabled.) */ -#define ISA_HAS_PREFETCHX ISA_HAS_FP4 +#define ISA_HAS_PREFETCHX (ISA_HAS_FP4 \ + || TARGET_LOONGSON_EXT \ + || TARGET_LOONGSON_EXT2) /* True if trunc.w.s and trunc.w.d are real (not synthetic) instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d @@ -1379,6 +1391,7 @@ struct mips_cpu_info { %{mmsa} %{mno-msa} \ %{mloongson-mmi} %{mno-loongson-mmi} \ %{mloongson-ext} %{mno-loongson-ext} \ +%{mloongson-ext2} %{mno-loongson-ext2} \ %{msmartmips} %{mno-smartmips} \ %{mmt} %{mno-mt} \ %{mfix-rm7000} %{mno-fix-rm7000} \ diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 4b7a627b7a6..8358218d8ac 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -3146,6 +3146,23 @@ [(set_attr "type" "clz") (set_attr "mode" "")]) +;; +;; ................... +;; +;; Count tailing zeroes. +;; +;; ................... +;; + +(define_insn "ctz2" + [(set (match_operand:GPR 0 "register_operand" "=d") + (ctz:GPR (match_operand:GPR 1 "register_operand" "d")))] + "ISA_HAS_CTZ_CTO" + "ctz\t%0,%1" + [(set_attr "type" "clz") + (set_attr "mode" "")]) + + ;; ;; ................... ;; @@ -7136,13 +7153,20 @@ (match_operand 2 "const_int_operand" "n"))] "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS" { - if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT) + if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || TARGET_LOONGSON_EXT2) { - /* Loongson 2[ef] and Loongson 3a use load to $0 for prefetching. */ + /* Loongson ext2 implementation pref insnstructions. */ + if (TARGET_LOONGSON_EXT2) + { + operands[1] = mips_loongson_ext2_prefetch_cookie (operands[1], + operands[2]); + return "pref\t%1, %a0"; + } + /* Loongson 2[ef] and Loongson ext use load to $0 for prefetching. */ if (TARGET_64BIT) - return "ld\t$0,%a0"; + return "ld\t$0,%a0"; else - return "lw\t$0,%a0"; + return "lw\t$0,%a0"; } operands[1] = mips_prefetch_cookie (operands[1], operands[2]); return "pref\t%1,%a0"; @@ -7156,6 +7180,21 @@ (match_operand 3 "const_int_operand" "n"))] "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" { + if (TARGET_LOONGSON_EXT || TARGET_LOONGSON_EXT2) + { + /* Loongson ext2 implementation pref insnstructions. */ + if (TARGET_LOONGSON_EXT2) + { + operands[2] = mips_loongson_ext2_prefetch_cookie (operands[2], + operands[3]); + return "prefx\t%2,%1(%0)"; + } + /* Loongson Loongson ext use index load to $0 for prefetching. */ + if (TARGET_64BIT) + return "gsldx\t$0,0(%0,%1)"; + else + return "gslwx\t$0,0(%0,%1)"; + } operands[2] = mips_prefetch_cookie (operands[2], operands[3]); return "prefx\t%2,%1(%0)"; } diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt index a8fe8db3c66..c0c8005b025 100644 --- a/gcc/config/mips/mips.opt +++ b/gcc/config/mips/mips.opt @@ -467,3 +467,7 @@ Use Loongson MultiMedia extensions Instructions (MMI) instructions. mloongson-ext Target Report Mask(LOONGSON_EXT) Use Loongson EXTension (EXT) instructions. + +mloongson-ext2 +Target Report Mask(LOONGSON_EXT2) +Use Loongson EXTension R2 (EXT2) instructions. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index ae92323eb06..d36a15a34ef 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -922,6 +922,7 @@ Objective-C and Objective-C++ Dialects}. -mmsa -mno-msa @gol -mloongson-mmi -mno-loongson-mmi @gol -mloongson-ext -mno-loongson-ext @gol +-mloongson-ext2 -mno-loongson-ext2 @gol -mfpu=@var{fpu-type} @gol -msmartmips -mno-smartmips @gol -mpaired-single -mno-paired-single -mdmx -mno-mdmx @gol @@ -21301,6 +21302,12 @@ Use (do not use) the MIPS Loongson MultiMedia extensions Instructions (MMI). @opindex mno-loongson-ext Use (do not use) the MIPS Loongson EXTensions (EXT) instructions. +@item -mloongson-ext2 +@itemx -mno-loongson-ext2 +@opindex mloongson-ext2 +@opindex mno-loongson-ext2 +Use (do not use) the MIPS Loongson EXTensions r2 (EXT2) instructions. + @item -mlong64 @opindex mlong64 Force @code{long} types to be 64 bits wide. See @option{-mlong32} for diff --git a/gcc/testsuite/gcc.target/mips/loongson-ctz.c b/gcc/testsuite/gcc.target/mips/loongson-ctz.c new file mode 100644 index 00000000000..8df66a00dc1 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/loongson-ctz.c @@ -0,0 +1,11 @@ +/* Test cases for Loongson EXT2 instrutions. */ + +/* { dg-do compile } */ +/* { dg-options "-mloongson-ext2" } */ + +unsigned int foo(unsigned int x) +{ + return __builtin_ctz (x); +} + +/* { dg-final { scan-assembler "ctz\t" } } */ diff --git a/gcc/testsuite/gcc.target/mips/loongson-dctz.c b/gcc/testsuite/gcc.target/mips/loongson-dctz.c new file mode 100644 index 00000000000..8c47433459f --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/loongson-dctz.c @@ -0,0 +1,11 @@ +/* Test cases for Loongson EXT2 instrutions. */ + +/* { dg-do compile } */ +/* { dg-options "-mloongson-ext2" } */ + +unsigned long long foo(unsigned long long x) +{ + return __builtin_ctzl (x); +} + +/* { dg-final { scan-assembler "dctz\t" } } */ diff --git a/gcc/testsuite/gcc.target/mips/mips.exp b/gcc/testsuite/gcc.target/mips/mips.exp index ceb86cc0276..e70d416d0dd 100644 --- a/gcc/testsuite/gcc.target/mips/mips.exp +++ b/gcc/testsuite/gcc.target/mips/mips.exp @@ -298,6 +298,7 @@ foreach option { msa loongson-mmi loongson-ext + loongson-ext2 } { lappend mips_option_groups $option "-m(no-|)$option" } -- 2.18.0