From patchwork Fri Sep 6 19:31:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 1159196 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-508535-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="jGZN9Hln"; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="YnwZc1iW"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46Q7424461z9sDB for ; Sat, 7 Sep 2019 05:32:16 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:references:in-reply-to:from:date:message-id :subject:to:cc:content-type; q=dns; s=default; b=uB1+3H5QvcNI1Vd RTc+KDXqhij0X4oGJlEZuxEd8NVagruc6tY3NAthqO5ivFmNrIcSetwH/D2Rw5tj 52a0b+gtblfLP8ThwEVuaobbKLBDQUZX+7QSWybVslWwEmLTnvZAA3Z7jntjlzJo AGpq8/VUpf3TZV1HTKuIyMM0jKOI= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:references:in-reply-to:from:date:message-id :subject:to:cc:content-type; s=default; bh=Rtjwj7Anv3Jo2tmSr69k7 6WCwyc=; b=jGZN9HlnNV5qRYB+mX1DV79Kq33fsVB0ULjzyovOXnA7J+n2cEL+j mmO0/rSuKyou/tV2ChGUEAeeuwrRV8GpxL+UozD5z9B0qwj9vzxjjk0p3X1941X7 yLASdFMHvluGH2+YSocIWnoqKm/NZzifsKIaT6htWSY5pB2wQ4enpE= Received: (qmail 81724 invoked by alias); 6 Sep 2019 19:32:09 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 81715 invoked by uid 89); 6 Sep 2019 19:32:09 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-15.3 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.1 spammy=HX-Languages-Length:2811, atom, regularly X-HELO: mail-io1-f41.google.com Received: from mail-io1-f41.google.com (HELO mail-io1-f41.google.com) (209.85.166.41) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 06 Sep 2019 19:32:08 +0000 Received: by mail-io1-f41.google.com with SMTP id k13so50285ioj.1 for ; Fri, 06 Sep 2019 12:32:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=LSFRmhx2/zAyzOBD2WQ0xEbbTawRrj4zgNAgPnpzEb4=; b=YnwZc1iWdOjeQI7f5UgHBSkDQfkpMuFJglEREx+t+I93cw6Cm7D9hejpO4Zrvj3xVE gqGY7iNKjS/8HCO72qFGilS7jkfDfpO9ciyrWQaKnWuDAsAx7+/UW7lmg94iISR9zzpZ LH1UF/TT6ecSW7gYDOUqKf4tqSZRLknAWJFKQMI/nQPAvUWe5UH1h2yldxJgjO0+zgzw Jba1g4Xw7C549Z0tofaU5Uwj0d6VOl3oGmYFDn4BFlE4yjWvd6YaOzxcsYIlxoobIZLW R/T0OGoKuQ5ln9DbBKlrt0WiWuTUqzlxPitI+do4SHrjvIiNnCe4pYhoq6uyS0JiJrem /DbA== MIME-Version: 1.0 References: <20190831005151.GD9227@bubble.grove.modra.org> In-Reply-To: From: Uros Bizjak Date: Fri, 6 Sep 2019 21:31:54 +0200 Message-ID: Subject: [PATCH, i386]: Fix PR 91654: Runtime SPEC regression on Haswell To: Hongtao Liu Cc: Richard Biener , Jakub Jelinek , Alan Modra , "gcc-patches@gcc.gnu.org" On Thu, Sep 5, 2019 at 10:53 AM Uros Bizjak wrote: > > On Thu, Sep 5, 2019 at 7:47 AM Hongtao Liu wrote: > > > > Change cost from 2->6 got > > ------------- > > 531.deepsjeng_r 9.64% > > 548.exchange_r 10.24% > > 557.xc_r 7.99% > > 508.namd_r 1.08% > > 527.cam4_r 6.91% > > 553.nab_r 3.06% > > ------------ > > > > for 531,548,557,527, even better comparing to version before regression. > > for 508,533, still little regressions comparing to version before regression. > > Good, that brings us into "noise" region. > > Based on these results and other findings, I propose the following solution: > > - The inter-regset move costs of architectures, that have been defined > before r125951 remain the same. These are: size, i386, i486, pentium, > pentiumpro, geode, k6, athlon, k8, amdfam10, pentium4 and nocona. > - bdver, btver1 and btver2 have costs higher than 8, so they are not affected. > - lakemont, znver1, znver2, atom, slm, intel and generic costs have > inter-regset costs above intra-regset and below or equal memory > load/store cost, should remain as they are. Additionally, intel and > generic costs are regularly re-tuned. > - only skylake and core costs remain problematic > > So, I propose to raise XMM<->intreg costs of skylake and core > architectures to 6 to solve the regression. These can be fine-tuned > later, we are now able to change the cost for RA independently of RTX > costs. Also, the RA cost can be asymmetrical. > > Attached patch implements the proposal. If there are no other > proposals or discussions, I plan to commit it on Friday. 2019-09-06 Uroš Bizjak PR target/91654 * config/i386/x86-tune-costs.h (skylake_cost): Raise the cost of SSE->integer and integer->SSE moves from 2 to 6. (core_cost): Ditto. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Committed to mainline SVN. Uros. diff --git a/gcc/config/i386/x86-tune-costs.h b/gcc/config/i386/x86-tune-costs.h index 3381b8bf143c..00edece3eb68 100644 --- a/gcc/config/i386/x86-tune-costs.h +++ b/gcc/config/i386/x86-tune-costs.h @@ -1610,7 +1610,7 @@ struct processor_costs skylake_cost = { in 32,64,128,256 and 512-bit */ {8, 8, 8, 12, 24}, /* cost of storing SSE registers in 32,64,128,256 and 512-bit */ - 2, 2, /* SSE->integer and integer->SSE moves */ + 6, 6, /* SSE->integer and integer->SSE moves */ /* End of register allocator costs. */ }, @@ -2555,7 +2555,7 @@ struct processor_costs core_cost = { in 32,64,128,256 and 512-bit */ {6, 6, 6, 6, 12}, /* cost of storing SSE registers in 32,64,128,256 and 512-bit */ - 2, 2, /* SSE->integer and integer->SSE moves */ + 6, 6, /* SSE->integer and integer->SSE moves */ /* End of register allocator costs. */ },