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[i386] : Also use and split insns with SSE operands for 32bit MMX targets

Message ID CAFULd4bMcZtOxUgSS4mgORVgG89nrADRX1i-vFUH5Zg0NM-UBQ@mail.gmail.com
State New
Headers show
Series [i386] : Also use and split insns with SSE operands for 32bit MMX targets | expand

Commit Message

Uros Bizjak July 1, 2019, 6:44 p.m. UTC 
Attached patch uses and splits a couple of instructions with SSE
operands for 32bit MMX targets.

2019-07-01  Uroš Bizjak  <ubizjak@gmail.com>

    * config/i386/i386.md ("isa" attribute): Add sse_noavx.
    ("enabled" attribute): Handle sse_noavx isa attribute.
    * config/i386/mmx.md (*vec_dupv2sf): Add "isa" attribute.
    Use TARGET_SSE && SSE_REGNO_P in split condition.
    (*vec_dupv2sf): Ditto.

Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.

Committed to mainline SVN.

Uros.
diff mbox series

Patch

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index c362a72411a2..c401deb5eb00 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -794,7 +794,7 @@ 
 
 ;; Used to control the "enabled" attribute on a per-instruction basis.
 (define_attr "isa" "base,x64,x64_sse2,x64_sse4,x64_sse4_noavx,x64_avx,nox64,
-		    sse2,sse2_noavx,sse3,sse4,sse4_noavx,avx,noavx,
+		    sse_noavx,sse2,sse2_noavx,sse3,sse4,sse4_noavx,avx,noavx,
 		    avx2,noavx2,bmi,bmi2,fma4,fma,avx512f,noavx512f,
 		    avx512bw,noavx512bw,avx512dq,noavx512dq,
 		    avx512vl,noavx512vl,x64_avx512dq,x64_avx512bw"
@@ -820,6 +820,8 @@ 
 	   (symbol_ref "TARGET_64BIT && TARGET_AVX512BW")
 	 (eq_attr "isa" "nox64") (symbol_ref "!TARGET_64BIT")
 	 (eq_attr "isa" "sse2") (symbol_ref "TARGET_SSE2")
+	 (eq_attr "isa" "sse_noavx")
+	   (symbol_ref "TARGET_SSE && !TARGET_AVX")
 	 (eq_attr "isa" "sse2_noavx")
 	   (symbol_ref "TARGET_SSE2 && !TARGET_AVX")
 	 (eq_attr "isa" "sse3") (symbol_ref "TARGET_SSE3")
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 70413349390c..9ff86ba0eecc 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -590,12 +590,16 @@ 
    punpckldq\t%0, %0
    #
    #"
-  "TARGET_MMX_WITH_SSE && reload_completed"
+  "TARGET_SSE && reload_completed
+   && SSE_REGNO_P (REGNO (operands[0]))"
   [(set (match_dup 0)
 	(vec_duplicate:V4SF (match_dup 1)))]
-  "operands[0] = lowpart_subreg (V4SFmode, operands[0],
-				 GET_MODE (operands[0]));"
-  [(set_attr "mmx_isa" "native,sse_noavx,avx")
+{
+  operands[0] = lowpart_subreg (V4SFmode, operands[0],
+				GET_MODE (operands[0]));
+}
+  [(set_attr "isa" "*,sse_noavx,avx")
+   (set_attr "mmx_isa" "native,*,*")
    (set_attr "type" "mmxcvt,ssemov,ssemov")
    (set_attr "mode" "DI,TI,TI")])
 
@@ -1560,12 +1564,16 @@ 
    #
    #
    #"
-  "TARGET_MMX_WITH_SSE && reload_completed"
+  "TARGET_SSE && reload_completed
+   && SSE_REGNO_P (REGNO (operands[0]))"
   [(set (match_dup 0)
 	(vec_duplicate:V4SI (match_dup 1)))]
-  "operands[0] = lowpart_subreg (V4SImode, operands[0],
-				 GET_MODE (operands[0]));"
-  [(set_attr "mmx_isa" "native,sse_noavx,avx,avx")
+{
+  operands[0] = lowpart_subreg (V4SImode, operands[0],
+				GET_MODE (operands[0]));
+}
+  [(set_attr "isa" "*,sse_noavx,avx,avx")
+   (set_attr "mmx_isa" "native,*,*,*")
    (set_attr "type" "mmxcvt,ssemov,ssemov,ssemov")
    (set_attr "mode" "DI,TI,TI,TI")])