From patchwork Sat May 11 08:23:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 1098386 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-500485-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="v94jEi6b"; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="s59+yjXX"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 451Kpx2v1kz9sB8 for ; Sat, 11 May 2019 18:23:30 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; q= dns; s=default; b=cPAoVlxlTRaCoeEc7txgL9O1IvOTOSg1T1vsa1n3iN1uQn i3BsHaoXf4OihvBd9AFpqauJtWzRoKg2JTdaE69gwnlSyeA8tY5cTNlhb5DtqbcT RHL1ce9KAIXGAwCOUfWMXwJhk+ZEXwewpKIVGqDUL2DVeV6adf6zNrRrtnl1A= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; s= default; bh=SCYNUZjb3eAdTAycZpk4a8c/Hso=; b=v94jEi6bb4B2A9oCudCh tz+69F0zKjkkKdtWLlXJX6keeg32yM593PcxnFnCp2ltBDF1mtPi8BE95xMi9qU+ 0EtvonvonCjwM1fP0dk9SEEJiJqHS3tj5zA8I9xLMSGU3VcD2oGxGa/NA3PfH/Z6 i2qEwXvDs2xKDhNGDErniS8= Received: (qmail 121388 invoked by alias); 11 May 2019 08:23:22 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 121377 invoked by uid 89); 11 May 2019 08:23:22 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: =?iso-8859-1?q?No=2C_score=3D-14=2E5_required=3D5=2E?= =?iso-8859-1?q?0_tests=3DAWL=2CBAYES_00=2CFREEMAIL_FROM=2CGIT_PATC?= =?iso-8859-1?q?H_0=2CGIT_PATCH_1=2CGIT_PATCH_2=2CGIT_PATCH_3=2CRCV?= =?iso-8859-1?q?D_IN_DNSWL_NONE=2CSPF_PASS_autolearn=3Dham_version?= =?iso-8859-1?q?=3D3=2E3=2E1_spammy=3DTARGET_64BIT=2C_Uro=C5=A1=2C_?= =?iso-8859-1?q?uro=C5=A1=2C_Uro?= X-HELO: mail-it1-f172.google.com Received: from mail-it1-f172.google.com (HELO mail-it1-f172.google.com) (209.85.166.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sat, 11 May 2019 08:23:20 +0000 Received: by mail-it1-f172.google.com with SMTP id m141so11695958ita.3 for ; Sat, 11 May 2019 01:23:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:from:date:message-id:subject:to; bh=gSZ59Z08f8gfa3B5rNuPhrQtVvFnr1vaOv3ItJxz11A=; b=s59+yjXX3hT73X+aNj1vNgU16iVlQr/wXGdkchld5wfNv2aaEtU+7tVfRgSzyeVwPL +vKtgvtjn1HM7Z67uLRLdfWisLchCGQ/WPN1+peqkxO7440ky67gFlpJUcVFVqAWyzo4 yV4+VHck6oolH7JQ8s80abVKWKv2yxfIHoVbxWfWCZkSkMY3T2m92fhWSWmz0emhCYNp rvRE87OIIbalQquluY4T7PukYzlFevbSMOVAWGXhmfLdh3nrGt7Ni1bMTF5/N3Oh4wxd 4fkjXM2rdik7YmrSziMtHlOZm/d5/oVQL77qvprW/oK9hCrQ+nNHMCE68uAIh/DC/k16 Y1rA== MIME-Version: 1.0 From: Uros Bizjak Date: Sat, 11 May 2019 10:23:07 +0200 Message-ID: Subject: [PATCH, i386]: Use pinsrd to move DImode value to xmm reg To: "gcc-patches@gcc.gnu.org" We can use pinsrd when moving DImode value from integer register pair to xmm reg for 32bit SSE4.1 targets. 2019-05-11 Uroš Bizjak * config/i386/i386.md (floatdi2_i387_with_xmm): Use pinsrd for TARGET_SSE4_1. * config/i386/sse.md (movdi_to_sse): Ditto. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Committed to mainline SVN. Uros. diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 46277f158bb3..1886715fe77e 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -5117,12 +5117,12 @@ }) (define_insn_and_split "floatdi2_i387_with_xmm" - [(set (match_operand:X87MODEF 0 "register_operand" "=f") + [(set (match_operand:X87MODEF 0 "register_operand" "=f,f") (float:X87MODEF - (match_operand:DI 1 "register_operand" "r"))) - (clobber (match_scratch:V4SI 3 "=x")) - (clobber (match_scratch:V4SI 4 "=x")) - (clobber (match_operand:DI 2 "memory_operand" "=m"))] + (match_operand:DI 1 "register_operand" "r,r"))) + (clobber (match_operand:DI 2 "memory_operand" "=m,m")) + (clobber (match_scratch:V4SI 3 "=x,x")) + (clobber (match_scratch:V4SI 4 "=X,x"))] "!TARGET_64BIT && TARGET_INTER_UNIT_MOVES_TO_VEC && TARGET_80387 && X87_ENABLE_FLOAT (mode, DImode) && TARGET_SSE2 && optimize_function_for_speed_p (cfun)" @@ -5135,14 +5135,21 @@ Assemble the 64-bit DImode value in an xmm register. */ emit_insn (gen_sse2_loadld (operands[3], CONST0_RTX (V4SImode), gen_lowpart (SImode, operands[1]))); - emit_insn (gen_sse2_loadld (operands[4], CONST0_RTX (V4SImode), - gen_highpart (SImode, operands[1]))); - emit_insn (gen_vec_interleave_lowv4si (operands[3], operands[3], - operands[4])); - + if (TARGET_SSE4_1) + emit_insn (gen_sse4_1_pinsrd (operands[3], operands[3], + gen_highpart (SImode, operands[1]), + GEN_INT (2))); + else + { + emit_insn (gen_sse2_loadld (operands[4], CONST0_RTX (V4SImode), + gen_highpart (SImode, operands[1]))); + emit_insn (gen_vec_interleave_lowv4si (operands[3], operands[3], + operands[4])); + } operands[3] = gen_lowpart (DImode, operands[3]); } - [(set_attr "type" "multi") + [(set_attr "isa" "sse4,*") + (set_attr "type" "multi") (set_attr "mode" "") (set_attr "unit" "i387") (set_attr "fp_int_src" "true")]) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 6b8298d957ed..a223a58ed540 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -1300,10 +1300,10 @@ ;; from there. (define_insn_and_split "movdi_to_sse" - [(set (match_operand:V4SI 0 "register_operand" "=?x,x") - (unspec:V4SI [(match_operand:DI 1 "nonimmediate_operand" "r,m")] + [(set (match_operand:V4SI 0 "register_operand" "=x,x,?x") + (unspec:V4SI [(match_operand:DI 1 "nonimmediate_operand" "r,m,r")] UNSPEC_MOVDI_TO_SSE)) - (clobber (match_scratch:V4SI 2 "=&x,X"))] + (clobber (match_scratch:V4SI 2 "=X,X,&x"))] "!TARGET_64BIT && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_TO_VEC" "#" "&& reload_completed" @@ -1315,18 +1315,26 @@ Assemble the 64-bit DImode value in an xmm register. */ emit_insn (gen_sse2_loadld (operands[0], CONST0_RTX (V4SImode), gen_lowpart (SImode, operands[1]))); - emit_insn (gen_sse2_loadld (operands[2], CONST0_RTX (V4SImode), - gen_highpart (SImode, operands[1]))); - emit_insn (gen_vec_interleave_lowv4si (operands[0], operands[0], - operands[2])); - } + if (TARGET_SSE4_1) + emit_insn (gen_sse4_1_pinsrd (operands[0], operands[0], + gen_highpart (SImode, operands[1]), + GEN_INT (2))); + else + { + emit_insn (gen_sse2_loadld (operands[2], CONST0_RTX (V4SImode), + gen_highpart (SImode, operands[1]))); + emit_insn (gen_vec_interleave_lowv4si (operands[0], operands[0], + operands[2])); + } + } else if (memory_operand (operands[1], DImode)) emit_insn (gen_vec_concatv2di (gen_lowpart (V2DImode, operands[0]), operands[1], const0_rtx)); else gcc_unreachable (); DONE; -}) +} + [(set_attr "isa" "sse4,*,*")]) (define_split [(set (match_operand:V4SF 0 "register_operand")