From patchwork Mon Jul 29 23:00:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 1138707 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-505779-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="Fo5o4V+E"; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="S6ipDVPi"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45yFXx2YF7z9sBZ for ; Tue, 30 Jul 2019 09:01:03 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; q= dns; s=default; b=sSmKhFPxC3R8s6DHFIKWn2/wFNdmr6NNPmkr6MIPgtpFPS RSeEmGWbBnkZe2FCA9JCcZRP7dM4bj2t3v8GGML3e3ZZE453THHhz3mvo10LnFYc 6Z8TwaHXwOd19I59rRwvh9HKRlKlaciLH+eobqsuQ3uoHcDH9p3eW37TbvWKY= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; s= default; bh=3f6OfP8hvOOU4bdxV5yDQyMAoHg=; b=Fo5o4V+EKFqZX+CHbRNc zAr4tZagEOEP/P+YIBy18vsiDzgKO9MqVa0fR/mWZI7+epaEQ7AXAx6YlsGzoSVp 3+XHzFur74hHxaxaVPipHKq+7AlnLAkzr4PAs4nZF5BG/NSzmTBCDnOmFDC2Lut7 k0B31jj1CW2ZTfRXe2xTw1Y= Received: (qmail 79041 invoked by alias); 29 Jul 2019 23:00:55 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 79033 invoked by uid 89); 29 Jul 2019 23:00:55 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-7.5 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.1 spammy=MODE, HX-Languages-Length:4401 X-HELO: mail-io1-f47.google.com Received: from mail-io1-f47.google.com (HELO mail-io1-f47.google.com) (209.85.166.47) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 29 Jul 2019 23:00:53 +0000 Received: by mail-io1-f47.google.com with SMTP id k20so123772935ios.10 for ; Mon, 29 Jul 2019 16:00:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:from:date:message-id:subject:to; bh=6WK5tdhVh4XxjiG6LJIkYMsi9SWa4hcAJ2p3nmFV1qI=; b=S6ipDVPio96eX1oWEwZlSjkek/YtpWDtD87Tvfr27pfgd3ZeQ1S6T4zWlmXtgtTbvX S+j5pAg4RYK7eiPMixHaIU0sxwwIefzQGIpCT6hL6f9JB9vsGIlfA6vFNUO772p3X52u 973lufiG3kJjhRqxDQTqSGXxZ/5ZFf7l424JnarLlt1gqxtK1Mk0136XC8HOhdrZTRVg /lg8VnDoPit5BUtdHXb3oJRVa4zoRYEwDKbSlIzEI5EADjRC69m9UMZIUUw2jOHeRGEb C23OWSnE1hlBPrgpFiqu3hL6IAFpX5cDM87hU2TBUB8mdz7SmPg0Cp3CcIpZe2awhzqH e7Sw== MIME-Version: 1.0 From: Uros Bizjak Date: Tue, 30 Jul 2019 01:00:40 +0200 Message-ID: Subject: [PATCH, i386]: Some further movstrict cleanups To: "gcc-patches@gcc.gnu.org" Attached patch allows only SUBREGs as output operands to movstrict expander and further allows only register operand outputs in various corresponding splitters. This enforces the restriction, as documented for STRICT_LOW_PART RTX: This expression code is used in only one context: as the destination operand of a 'set' expression. In addition, the operand of this expression must be a non-paradoxical 'subreg' expression. Additionally, the patch removes post-reload calls to movstrict expander and consequently constructs RTXes involving STRICT_LOW_PART with hard registers "by hand". 2019-07-30 Uroš Bizjak * config/i386/i386.md (movstrict): Use register_operand predicate for operand 0. Add expander condition. Assert that operand 0 is a SUBREG RTX. (*movstrict_1): Use register_operand predicate for operand 0. Update operand constraints and insn condition. (zero_extendsi2_and): Do not call gen_movstrict. (zero_extendqihi2_and): Do not call gen_movstrictqi. (*setcc_qi_slp): Use register_operand predicate for operand 0. Update operand 0 constraints. (setcc_qi_slp splitters): Use register_operand predicate for operand 0. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Committed to mainline SVN. Uros. Index: config/i386/i386.md =================================================================== --- config/i386/i386.md (revision 273873) +++ config/i386/i386.md (working copy) @@ -2786,26 +2786,20 @@ (set_attr "bdver1_decode" "double")]) (define_expand "movstrict" - [(set (strict_low_part (match_operand:SWI12 0 "nonimmediate_operand")) + [(set (strict_low_part (match_operand:SWI12 0 "register_operand")) (match_operand:SWI12 1 "general_operand"))] - "" + "!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)" { - if (TARGET_PARTIAL_REG_STALL && optimize_function_for_speed_p (cfun)) + gcc_assert (SUBREG_P (operands[0])); + if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (operands[0]))) != MODE_INT) FAIL; - if (SUBREG_P (operands[0]) - && GET_MODE_CLASS (GET_MODE (SUBREG_REG (operands[0]))) != MODE_INT) - FAIL; - /* Don't generate memory->memory moves, go through a register */ - if (MEM_P (operands[0]) && MEM_P (operands[1])) - operands[1] = force_reg (mode, operands[1]); }) (define_insn "*movstrict_1" [(set (strict_low_part - (match_operand:SWI12 0 "nonimmediate_operand" "+m,")) - (match_operand:SWI12 1 "general_operand" "n,m"))] - "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)) - && !(MEM_P (operands[0]) && MEM_P (operands[1]))" + (match_operand:SWI12 0 "register_operand" "+")) + (match_operand:SWI12 1 "general_operand" "mn"))] + "!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)" "mov{}\t{%1, %0|%0, %1}" [(set_attr "type" "imov") (set_attr "mode" "")]) @@ -4011,8 +4005,10 @@ ix86_expand_clear (operands[0]); gcc_assert (!TARGET_PARTIAL_REG_STALL); - emit_insn (gen_movstrict - (gen_lowpart (mode, operands[0]), operands[1])); + emit_insn (gen_rtx_SET + (gen_rtx_STRICT_LOW_PART + (VOIDmode, gen_lowpart (mode, operands[0])), + operands[1])); DONE; } @@ -4063,8 +4059,10 @@ ix86_expand_clear (operands[0]); gcc_assert (!TARGET_PARTIAL_REG_STALL); - emit_insn (gen_movstrictqi - (gen_lowpart (QImode, operands[0]), operands[1])); + emit_insn (gen_rtx_SET + (gen_rtx_STRICT_LOW_PART + (VOIDmode, gen_lowpart (QImode, operands[0])), + operands[1])); DONE; } @@ -11835,7 +11833,7 @@ (set_attr "mode" "QI")]) (define_insn "*setcc_qi_slp" - [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm")) + [(set (strict_low_part (match_operand:QI 0 "register_operand" "+q")) (match_operator:QI 1 "ix86_comparison_operator" [(reg FLAGS_REG) (const_int 0)]))] "" @@ -11864,7 +11862,7 @@ }) (define_split - [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand")) + [(set (strict_low_part (match_operand:QI 0 "register_operand")) (ne:QI (match_operator 1 "ix86_comparison_operator" [(reg FLAGS_REG) (const_int 0)]) (const_int 0)))] @@ -11896,7 +11894,7 @@ }) (define_split - [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand")) + [(set (strict_low_part (match_operand:QI 0 "register_operand")) (eq:QI (match_operator 1 "ix86_comparison_operator" [(reg FLAGS_REG) (const_int 0)]) (const_int 0)))]