From patchwork Wed Jul 12 19:11:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 1806969 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=WuSu7sTO; dkim-atps=neutral Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4R1S6n47Myz20bt for ; Thu, 13 Jul 2023 05:12:30 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 7DECC385770D for ; Wed, 12 Jul 2023 19:12:26 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 7DECC385770D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1689189146; bh=cPfaz/Vo89epfhKnbPGb2p/yJlAHZoH4Ij4Y0rNJQkE=; h=Date:Subject:To:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=WuSu7sTO8+UA+npLQhkBsG0AGil8GTRyaOWdmvr9l2qoxDHtul2Qxkoe4vWcMKCHM YcmRVgVWH8svZGMnUnFYi5dOIBD4Fpvb53mT4j41Wo4niFzvrNYaAESsVKEGX7x4oh kBp3v/RrSGr7OXeTG4P0dFrZdwkWROG7qKNcjFrI= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by sourceware.org (Postfix) with ESMTPS id 52CDB3858D20 for ; Wed, 12 Jul 2023 19:12:04 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 52CDB3858D20 Received: by mail-lf1-x12e.google.com with SMTP id 2adb3069b0e04-4fb7769f15aso12047142e87.0 for ; Wed, 12 Jul 2023 12:12:04 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689189122; x=1691781122; h=to:subject:message-id:date:from:mime-version:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=cPfaz/Vo89epfhKnbPGb2p/yJlAHZoH4Ij4Y0rNJQkE=; b=YnsqIP+QUrh9wft0moBwApW62uh9J5QYKrBRpyeEIt4qNBgM4w6/xKl6hsvGIzSnbp woNWjLL1v+PX3e5QBgoyV19YxwUCQcl6NciKMOSe90woPUJrZk5G2xACyca1q1tOjqpc JmqtVOxIgxruQ0hNTtTdDbM6bpmG7xW8fT3P/1MNwAzA1bJ8Yan0ArJgkttQHfVPecYL HXDjmLPHHp9roYCFo3yps1byDM43gurKSnYpkoXfxEQ5OXHonI82E26CoyofcHjFSOki Nl/QyYqhXhm9v1qnQRnD5c3tPbnt20/Iz5qC3VbcrsetuXRVwTQtJgIANUbcRZxyOsIS dhVg== X-Gm-Message-State: ABy/qLa0vQtt/esEc2f/2VCRDsb3f2nn2v2d1SYpYfAvDJrlulnsqjey s7RMwyeKLNzLv2C4GbO75CjrrL4onIJogqr8fTODITwZXDneUg== X-Google-Smtp-Source: APBJJlGub9g82Un3MP4jK+z06bMOmMO6WtLvJyBC8vDw7JCJDdHWSeAakDslVbxUD2rg+WiYGb6/+VAhl1l/hYiifpk= X-Received: by 2002:a05:6512:3e03:b0:4f8:b349:6938 with SMTP id i3-20020a0565123e0300b004f8b3496938mr20062547lfv.65.1689189122148; Wed, 12 Jul 2023 12:12:02 -0700 (PDT) MIME-Version: 1.0 Date: Wed, 12 Jul 2023 21:11:50 +0200 Message-ID: Subject: [committed] IRA+LRA: Change return type of predicate functions from int to bool To: "gcc-patches@gcc.gnu.org" X-Spam-Status: No, score=-7.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Uros Bizjak via Gcc-patches From: Uros Bizjak Reply-To: Uros Bizjak Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" gcc/ChangeLog: * ira.cc (equiv_init_varies_p): Change return type from int to bool and adjust function body accordingly. (equiv_init_movable_p): Ditto. (memref_used_between_p): Ditto. * lra-constraints.cc (valid_address_p): Ditto. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Uros. diff --git a/gcc/ira.cc b/gcc/ira.cc index 02dea5d49ee..a1860105c60 100644 --- a/gcc/ira.cc +++ b/gcc/ira.cc @@ -3075,7 +3075,7 @@ validate_equiv_mem_from_store (rtx dest, const_rtx set ATTRIBUTE_UNUSED, info->equiv_mem_modified = true; } -static int equiv_init_varies_p (rtx x); +static bool equiv_init_varies_p (rtx x); enum valid_equiv { valid_none, valid_combine, valid_reload }; @@ -3145,8 +3145,8 @@ validate_equiv_mem (rtx_insn *start, rtx reg, rtx memref) return valid_none; } -/* Returns zero if X is known to be invariant. */ -static int +/* Returns false if X is known to be invariant. */ +static bool equiv_init_varies_p (rtx x) { RTX_CODE code = GET_CODE (x); @@ -3162,14 +3162,14 @@ equiv_init_varies_p (rtx x) CASE_CONST_ANY: case SYMBOL_REF: case LABEL_REF: - return 0; + return false; case REG: return reg_equiv[REGNO (x)].replace == 0 && rtx_varies_p (x, 0); case ASM_OPERANDS: if (MEM_VOLATILE_P (x)) - return 1; + return true; /* Fall through. */ @@ -3182,24 +3182,24 @@ equiv_init_varies_p (rtx x) if (fmt[i] == 'e') { if (equiv_init_varies_p (XEXP (x, i))) - return 1; + return true; } else if (fmt[i] == 'E') { int j; for (j = 0; j < XVECLEN (x, i); j++) if (equiv_init_varies_p (XVECEXP (x, i, j))) - return 1; + return true; } - return 0; + return false; } -/* Returns nonzero if X (used to initialize register REGNO) is movable. +/* Returns true if X (used to initialize register REGNO) is movable. X is only movable if the registers it uses have equivalent initializations which appear to be within the same loop (or in an inner loop) and movable or if they are not candidates for local_alloc and don't vary. */ -static int +static bool equiv_init_movable_p (rtx x, int regno) { int i, j; @@ -3212,7 +3212,7 @@ equiv_init_movable_p (rtx x, int regno) return equiv_init_movable_p (SET_SRC (x), regno); case CLOBBER: - return 0; + return false; case PRE_INC: case PRE_DEC: @@ -3220,7 +3220,7 @@ equiv_init_movable_p (rtx x, int regno) case POST_DEC: case PRE_MODIFY: case POST_MODIFY: - return 0; + return false; case REG: return ((reg_equiv[REGNO (x)].loop_depth >= reg_equiv[regno].loop_depth @@ -3229,11 +3229,11 @@ equiv_init_movable_p (rtx x, int regno) && ! rtx_varies_p (x, 0))); case UNSPEC_VOLATILE: - return 0; + return false; case ASM_OPERANDS: if (MEM_VOLATILE_P (x)) - return 0; + return false; /* Fall through. */ @@ -3247,16 +3247,16 @@ equiv_init_movable_p (rtx x, int regno) { case 'e': if (! equiv_init_movable_p (XEXP (x, i), regno)) - return 0; + return false; break; case 'E': for (j = XVECLEN (x, i) - 1; j >= 0; j--) if (! equiv_init_movable_p (XVECEXP (x, i, j), regno)) - return 0; + return false; break; } - return 1; + return true; } static bool memref_referenced_p (rtx memref, rtx x, bool read_p); @@ -3370,7 +3370,7 @@ memref_referenced_p (rtx memref, rtx x, bool read_p) Callers should not call this routine if START is after END in the RTL chain. */ -static int +static bool memref_used_between_p (rtx memref, rtx_insn *start, rtx_insn *end) { rtx_insn *insn; @@ -3383,15 +3383,15 @@ memref_used_between_p (rtx memref, rtx_insn *start, rtx_insn *end) continue; if (memref_referenced_p (memref, PATTERN (insn), false)) - return 1; + return true; /* Nonconst functions may access memory. */ if (CALL_P (insn) && (! RTL_CONST_CALL_P (insn))) - return 1; + return true; } gcc_assert (insn == NEXT_INSN (end)); - return 0; + return false; } /* Mark REG as having no known equivalence. diff --git a/gcc/lra-constraints.cc b/gcc/lra-constraints.cc index 123ff662cbc..9bfc88149ff 100644 --- a/gcc/lra-constraints.cc +++ b/gcc/lra-constraints.cc @@ -329,20 +329,20 @@ in_mem_p (int regno) return get_reg_class (regno) == NO_REGS; } -/* Return 1 if ADDR is a valid memory address for mode MODE in address +/* Return true if ADDR is a valid memory address for mode MODE in address space AS, and check that each pseudo has the proper kind of hard reg. */ -static int +static bool valid_address_p (machine_mode mode ATTRIBUTE_UNUSED, rtx addr, addr_space_t as) { #ifdef GO_IF_LEGITIMATE_ADDRESS lra_assert (ADDR_SPACE_GENERIC_P (as)); GO_IF_LEGITIMATE_ADDRESS (mode, addr, win); - return 0; + return false; win: - return 1; + return true; #else return targetm.addr_space.legitimate_address_p (mode, addr, 0, as); #endif @@ -1624,7 +1624,7 @@ insert_move_for_subreg (rtx_insn **before, rtx_insn **after, rtx origreg, } } -static int valid_address_p (machine_mode mode, rtx addr, addr_space_t as); +static bool valid_address_p (machine_mode mode, rtx addr, addr_space_t as); static bool process_address (int, bool, rtx_insn **, rtx_insn **); /* Make reloads for subreg in operand NOP with internal subreg mode