From patchwork Wed May 22 18:43:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 1103508 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-501464-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="aTB48jf4"; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="fe+XpVSs"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 458M3D0gKrz9sCJ for ; Thu, 23 May 2019 04:43:35 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; q= dns; s=default; b=EXmaEd0ND/+Ucz/ndAYalVeGNv/oG2Y/5lVNfE58ZoECMk 9ok5qqarZyDePToV2pkWtKvh9CobYKsRg6fyLLRdUdUGbF9svXrG6nDib1V12V/X VanrPLlzFayYpgJGSvh5INBxPQNv15OvktWYOkKS7on4+IiNp4a1eHacTOoog= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; s= default; bh=O4HBbhGpV2pgcp+Rnw70BeDW+uo=; b=aTB48jf4NsYh5jdQAKFU cAxzc8dT7UwQ8FVKZBFFdb4iE9BwFqjE6UvUWVqwqYtMPrECB82Iqt+v4Sy5eBPx cau0JxjeT6SRZr8kdF18G/Zb1k08vMX189Zno/fkeWNyi9VGQN9sjQSiz/ul2t7H 1PHMrkOWgSL/KtMs7jBzVLA= Received: (qmail 42188 invoked by alias); 22 May 2019 18:43:29 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 42180 invoked by uid 89); 22 May 2019 18:43:28 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-14.7 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.1 spammy=OP1, OP0, GEN_INT, target_avx X-HELO: mail-it1-f179.google.com Received: from mail-it1-f179.google.com (HELO mail-it1-f179.google.com) (209.85.166.179) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 22 May 2019 18:43:27 +0000 Received: by mail-it1-f179.google.com with SMTP id u186so4695940ith.0 for ; Wed, 22 May 2019 11:43:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:from:date:message-id:subject:to; bh=zeuSBHgDwrQoTzV3c8ZYB2GcMCLTslyuqyJVSm99b48=; b=fe+XpVSsmkoEYb+P7d+DLrFXg3xV3yvR+UxZWbjd8fZUu4fOkYylcFnqrJx7FxF/NR 2gyJuhtQXErn8XaCwMrBNXXz3pWoGIU3JMFAuCBeJciJeoymC1HIvhYddOm3sk25IRnV 63n9hNqnBBFVfYxVZyuRPIfFGsf2iT5CGk9n8IZo56KQ7NslHDpR6/XphVaMcu09kG6e 87ITX31LoBBeuLFc/0QpKVrHSU9X3iBsIieSflML2IKoqsqInxd+ploaMI64aqPTl4A6 O4u2zD4NxrqNAGbnVPzQRIgbLY8J8rmOd8ji6W2qyv/xb0JJAo2xKs3lb7qzbXnZWNZG ZQaw== MIME-Version: 1.0 From: Uros Bizjak Date: Wed, 22 May 2019 20:43:14 +0200 Message-ID: Subject: [PATCH, i386]: Fix up sse_cvtpi2ps insn condition To: "gcc-patches@gcc.gnu.org" This pattern needs TARGET_MMX as it uses mmx registers. 2019-05-22 Uroš Bizjak * config/i386/sse.md (sse_cvtpi2ps): Use TARGET_MMX in insn condition. (+ some trivial code reorg parts). Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Committed to mainline SVN. Uros. diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index adad950fa04d..dc8dabfafc85 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -1521,8 +1521,7 @@ op = gen_rtx_VEC_SELECT (V8HImode, operands[1], mask); } - rtx insn = gen_rtx_SET (operands[0], op); - emit_insn (insn); + emit_insn (gen_rtx_SET (operands[0], op)); DONE; } [(set_attr "mmx_isa" "native,x64,x64_avx") diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 7e7b3417cfc8..7d48402ee9d9 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -5012,7 +5012,7 @@ (match_operand:V4SF 1 "register_operand" "0,0,Yv") (const_int 3))) (clobber (match_scratch:V4SF 3 "=X,x,Yv"))] - "TARGET_SSE || TARGET_MMX_WITH_SSE" + "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE" "@ cvtpi2ps\t{%2, %0|%0, %2} # @@ -5023,8 +5023,7 @@ rtx op2 = lowpart_subreg (V4SImode, operands[2], GET_MODE (operands[2])); /* Generate SSE2 cvtdq2ps. */ - rtx insn = gen_floatv4siv4sf2 (operands[3], op2); - emit_insn (insn); + emit_insn (gen_floatv4siv4sf2 (operands[3], op2)); /* Merge operands[3] with operands[0]. */ rtx mask, op1; @@ -5035,7 +5034,7 @@ GEN_INT (6), GEN_INT (7))); op1 = gen_rtx_VEC_CONCAT (V8SFmode, operands[3], operands[1]); op2 = gen_rtx_VEC_SELECT (V4SFmode, op1, mask); - insn = gen_rtx_SET (operands[0], op2); + emit_insn (gen_rtx_SET (operands[0], op2)); } else { @@ -5045,8 +5044,7 @@ GEN_INT (4), GEN_INT (5))); op1 = gen_rtx_VEC_CONCAT (V8SFmode, operands[0], operands[3]); op2 = gen_rtx_VEC_SELECT (V4SFmode, op1, mask); - insn = gen_rtx_SET (operands[0], op2); - emit_insn (insn); + emit_insn (gen_rtx_SET (operands[0], op2)); /* Swap bits 0:63 with bits 64:127. */ mask = gen_rtx_PARALLEL (VOIDmode, @@ -5055,9 +5053,8 @@ rtx dest = lowpart_subreg (V4SImode, operands[0], GET_MODE (operands[0])); op1 = gen_rtx_VEC_SELECT (V4SImode, dest, mask); - insn = gen_rtx_SET (dest, op1); + emit_insn (gen_rtx_SET (dest, op1)); } - emit_insn (insn); DONE; } [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") @@ -16356,14 +16353,12 @@ /* Emulate MMX palignrdi with SSE psrldq. */ rtx op0 = lowpart_subreg (V2DImode, operands[0], GET_MODE (operands[0])); - rtx insn; if (TARGET_AVX) - insn = gen_vec_concatv2di (op0, operands[2], operands[1]); + emit_insn (gen_vec_concatv2di (op0, operands[2], operands[1])); else { /* NB: SSE can only concatenate OP0 and OP1 to OP0. */ - insn = gen_vec_concatv2di (op0, operands[1], operands[2]); - emit_insn (insn); + emit_insn (gen_vec_concatv2di (op0, operands[1], operands[2])); /* Swap bits 0:63 with bits 64:127. */ rtx mask = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (4, GEN_INT (2), @@ -16372,9 +16367,8 @@ GEN_INT (1))); rtx op1 = lowpart_subreg (V4SImode, op0, GET_MODE (op0)); rtx op2 = gen_rtx_VEC_SELECT (V4SImode, op1, mask); - insn = gen_rtx_SET (op1, op2); + emit_insn (gen_rtx_SET (op1, op2)); } - emit_insn (insn); operands[0] = lowpart_subreg (V1TImode, op0, GET_MODE (op0)); } [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")