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Tue, 11 Jun 2024 10:01:45 -0700 (PDT) MIME-Version: 1.0 From: Uros Bizjak Date: Tue, 11 Jun 2024 19:01:33 +0200 Message-ID: Subject: [committed] i386: Use CMOV in .SAT_{ADD|SUB} expansion for TARGET_CMOV [PR112600] To: "gcc-patches@gcc.gnu.org" X-Spam-Status: No, score=-8.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org For TARGET_CMOV targets emit insn sequence involving conditional move. .SAT_ADD: addl %esi, %edi movl $-1, %eax cmovnc %edi, %eax ret .SAT_SUB: subl %esi, %edi movl $0, %eax cmovnc %edi, %eax ret PR target/112600 gcc/ChangeLog: * config/i386/i386.md (usadd3): Emit insn sequence involving conditional move for TARGET_CMOVE targets. (ussub3): Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/pr112600-a.c: Also scan for cmov. * gcc.target/i386/pr112600-b.c: Ditto. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Uros. diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index d69bc8d6e48..a64f2ad4f5f 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -9885,13 +9885,35 @@ (define_expand "usadd3" "" { rtx res = gen_reg_rtx (mode); - rtx msk = gen_reg_rtx (mode); rtx dst; emit_insn (gen_add3_cc_overflow_1 (res, operands[1], operands[2])); - emit_insn (gen_x86_movcc_0_m1_neg (msk)); - dst = expand_simple_binop (mode, IOR, res, msk, - operands[0], 1, OPTAB_WIDEN); + + if (TARGET_CMOVE) + { + rtx cmp = gen_rtx_GEU (VOIDmode, gen_rtx_REG (CCCmode, FLAGS_REG), + const0_rtx); + + if ( < GET_MODE_SIZE (SImode)) + { + dst = force_reg (mode, operands[0]); + emit_insn (gen_movsicc (gen_lowpart (SImode, dst), cmp, + gen_lowpart (SImode, res), constm1_rtx)); + } + else + { + dst = operands[0]; + emit_insn (gen_movcc (dst, cmp, res, constm1_rtx)); + } + } + else + { + rtx msk = gen_reg_rtx (mode); + + emit_insn (gen_x86_movcc_0_m1_neg (msk)); + dst = expand_simple_binop (mode, IOR, res, msk, + operands[0], 1, OPTAB_WIDEN); + } if (!rtx_equal_p (dst, operands[0])) emit_move_insn (operands[0], dst); @@ -9905,14 +9927,36 @@ (define_expand "ussub3" "" { rtx res = gen_reg_rtx (mode); - rtx msk = gen_reg_rtx (mode); rtx dst; emit_insn (gen_sub_3 (res, operands[1], operands[2])); - emit_insn (gen_x86_movcc_0_m1_neg (msk)); - msk = expand_simple_unop (mode, NOT, msk, NULL, 1); - dst = expand_simple_binop (mode, AND, res, msk, - operands[0], 1, OPTAB_WIDEN); + + if (TARGET_CMOVE) + { + rtx cmp = gen_rtx_GEU (VOIDmode, gen_rtx_REG (CCCmode, FLAGS_REG), + const0_rtx); + + if ( < GET_MODE_SIZE (SImode)) + { + dst = force_reg (mode, operands[0]); + emit_insn (gen_movsicc (gen_lowpart (SImode, dst), cmp, + gen_lowpart (SImode, res), const0_rtx)); + } + else + { + dst = operands[0]; + emit_insn (gen_movcc (dst, cmp, res, const0_rtx)); + } + } + else + { + rtx msk = gen_reg_rtx (mode); + + emit_insn (gen_x86_movcc_0_m1_neg (msk)); + msk = expand_simple_unop (mode, NOT, msk, NULL, 1); + dst = expand_simple_binop (mode, AND, res, msk, + operands[0], 1, OPTAB_WIDEN); + } if (!rtx_equal_p (dst, operands[0])) emit_move_insn (operands[0], dst); diff --git a/gcc/testsuite/gcc.target/i386/pr112600-a.c b/gcc/testsuite/gcc.target/i386/pr112600-a.c index fa122bc7a3f..2b084860451 100644 --- a/gcc/testsuite/gcc.target/i386/pr112600-a.c +++ b/gcc/testsuite/gcc.target/i386/pr112600-a.c @@ -1,7 +1,7 @@ /* PR target/112600 */ /* { dg-do compile } */ /* { dg-options "-O2" } */ -/* { dg-final { scan-assembler-times "sbb" 4 } } */ +/* { dg-final { scan-assembler-times "sbb|cmov" 4 } } */ unsigned char add_sat_char (unsigned char x, unsigned char y) diff --git a/gcc/testsuite/gcc.target/i386/pr112600-b.c b/gcc/testsuite/gcc.target/i386/pr112600-b.c index ea14bb9738b..ac4e26423b6 100644 --- a/gcc/testsuite/gcc.target/i386/pr112600-b.c +++ b/gcc/testsuite/gcc.target/i386/pr112600-b.c @@ -1,7 +1,7 @@ /* PR target/112600 */ /* { dg-do compile } */ /* { dg-options "-O2" } */ -/* { dg-final { scan-assembler-times "sbb" 4 } } */ +/* { dg-final { scan-assembler-times "sbb|cmov" 4 } } */ unsigned char sub_sat_char (unsigned char x, unsigned char y)