===================================================================
@@ -8723,20 +8723,6 @@
[(set_attr "type" "alu")
(set_attr "mode" "<MODE>")])
-(define_insn "*andqi_2_slp"
- [(set (reg FLAGS_REG)
- (compare (and:QI (match_operand:QI 0 "nonimmediate_operand" "+qm,q")
- (match_operand:QI 1 "nonimmediate_operand" "qn,m"))
- (const_int 0)))
- (set (strict_low_part (match_dup 0))
- (and:QI (match_dup 0) (match_dup 1)))]
- "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
- && ix86_match_ccmode (insn, CCNOmode)
- && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
- "and{b}\t{%1, %0|%0, %1}"
- [(set_attr "type" "alu1")
- (set_attr "mode" "QI")])
-
(define_insn "andqi_ext_1"
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q,Q")
(const_int 8)
@@ -9155,20 +9141,6 @@
[(set_attr "type" "alu")
(set_attr "mode" "SI")])
-(define_insn "*<code>qi_2_slp"
- [(set (reg FLAGS_REG)
- (compare (any_or:QI (match_operand:QI 0 "nonimmediate_operand" "+qm,q")
- (match_operand:QI 1 "general_operand" "qn,m"))
- (const_int 0)))
- (set (strict_low_part (match_dup 0))
- (any_or:QI (match_dup 0) (match_dup 1)))]
- "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
- && ix86_match_ccmode (insn, CCNOmode)
- && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
- "<logic>{q}\t{%1, %0|%0, %1}"
- [(set_attr "type" "alu1")
- (set_attr "mode" "QI")])
-
(define_insn "*<code><mode>_3"
[(set (reg FLAGS_REG)
(compare (any_or:SWI
These insn patterns are just too complex to ever match. Remove them. 2019-07-18 Uroš Bizjak <ubizjak@gmail.com> * config/i386/i386.md (*addqi_2_slp): Remove. (*<code>qi_2_slp): Ditto. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Committed to mainline SVN. For the reference, the correct form would be: --cut here-- (define_insn "*and<mode>_2_slp" [(set (reg FLAGS_REG) (compare (and:SWI12 (match_operand:SWI12 1 "nonimmediate_operand" "%0") (match_operand:SWI12 2 "general_operand" "<r>mn")) (const_int 0))) (set (strict_low_part (match_operand:SWI12 0 "register_operand" "+<r>")) (and:SWI12 (match_dup 1) (match_dup 2)))] "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)) && ix86_match_ccmode (insn, CCNOmode) /* FIXME: without this LRA can't reload this pattern, see PR82524. */ && (rtx_equal_p (operands[0], operands[1]) || rtx_equal_p (operands[0], operands[2]))" "and{<imodesuffix>}\t{%2, %0|%0, %2}" [(set_attr "type" "alu") (set_attr "mode" "<MODE>")]) (define_insn "*<code><mode>_2_slp" [(set (reg FLAGS_REG) (compare (any_or:SWI12 (match_operand:SWI12 1 "nonimmediate_operand" "%0") (match_operand:SWI12 2 "general_operand" "<r>mn")) (const_int 0))) (set (strict_low_part (match_operand:SWI12 0 "register_operand" "+<r>")) (any_or:SWI12 (match_dup 1) (match_dup 2)))] "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)) && ix86_match_ccmode (insn, CCNOmode) /* FIXME: without this LRA can't reload this pattern, see PR82524. */ && (rtx_equal_p (operands[0], operands[1]) || rtx_equal_p (operands[0], operands[2]))" "<logic>{<imodesuffix>}\t{%2, %0|%0, %2}" [(set_attr "type" "alu") (set_attr "mode" "<MODE>")]) --cut here-- Uros.