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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700083475; x=1700688275; h=to:subject:message-id:date:from:mime-version:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=/fA1Tls8BviAdx+ZPsvyjbJyzlU1Jt0lEKwrBH9GXas=; b=RvE0g8CZ3TFsQ6/X07T7Je3W9T1hkBd1jRb51jXh4psfnlT4b2F0NE8yQz/7Nc2XfL 6j0GMlxlrnmVCWRpMagttGNiR+Q23+QVpId9gKHChk9PhnWYFp0C0lmf6khclvyUW3LM /i0HUIItbmlChyN74/uM0DIJocE+omJlu7MTSizvPt55NEfhKF8HCfdzIji7BcKLMtJm Av6W5m+5T4+MAsYZFZwqlqc21dS0tzvtOMmApHYUunB0ZNtrASkJm1cqOXENDHj43w/2 cp7U7WbihKWvTEj3gf4U4RikDDODZF2iw5DZD0zUFDbO+JK3ZDWjqRSLwiKqVx3RbVOZ 3SKg== X-Gm-Message-State: AOJu0YxtJRo3CS9nZ1GRIqDVf1OnepWR3nASwx9rD8TeaoSal7Pgk4ZF Bn89qVcAWe/ZKSXSHTJXt145t7K0UJ8Ag6+eUxREsD4tAf6p5w== X-Google-Smtp-Source: AGHT+IHZ3WE81D7MzlzwU0Z7NzrcUrAc8+h1Zpfh63zHD2LBcDVqUZTvSOJuJptYsCR2Td2OE4MV60QkU8VSfaAT1UQ= X-Received: by 2002:ac2:546f:0:b0:509:f68:ed8 with SMTP id e15-20020ac2546f000000b005090f680ed8mr8479419lfn.61.1700083475296; Wed, 15 Nov 2023 13:24:35 -0800 (PST) MIME-Version: 1.0 From: Uros Bizjak Date: Wed, 15 Nov 2023 22:24:24 +0100 Message-ID: Subject: [committed] i386: Optimize strict_low_part QImode insn with high input registers To: "gcc-patches@gcc.gnu.org" X-Spam-Status: No, score=-7.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Following testcase: struct S1 { unsigned char val; unsigned char pad1; unsigned short pad2; }; struct S2 { unsigned char pad1; unsigned char val; unsigned short pad2; }; struct S1 test_add (struct S1 a, struct S2 b, struct S2 c) { a.val = b.val + c.val; return a; } compiles with -O2 to: movl %edi, %eax movzbl %dh, %edx movl %esi, %ecx movb %dl, %al addb %ch, %al The insert to %al can go directly from %dh: movl %edi, %eax movl %esi, %ecx movb %dh, %al addb %ch, %al Patch introduces strict_low_part QImode insn patterns with both of their input arguments extracted from high register. This invalid insn is split after reload to a lowpart insert from the high register and qi_ext_1_slp instruction. PR target/78904 gcc/ChangeLog: * config/i386/i386.md (*movstrictqi_ext_1): New insn pattern. (*addqi_ext_2_slp): New define_insn_and_split pattern. (*subqi_ext_2_slp): Ditto. (*qi_ext_2_slp): Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/pr78904-8.c: New test. * gcc.target/i386/pr78904-8a.c: New test. * gcc.target/i386/pr78904-8b.c: New test. * gcc.target/i386/pr78904-9.c: New test. * gcc.target/i386/pr78904-9a.c: New test. * gcc.target/i386/pr78904-9b.c: New test. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Uros. diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 32535621db4..26cdb21d3c0 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -3335,6 +3335,19 @@ (define_insn "*movstrict_xor" (set_attr "mode" "") (set_attr "length_immediate" "0")]) +(define_insn "*movstrictqi_ext_1" + [(set (strict_low_part + (match_operand:QI 0 "register_operand" "+Q")) + (subreg:QI + (match_operator:SWI248 2 "extract_operator" + [(match_operand 1 "int248_register_operand" "Q") + (const_int 8) + (const_int 8)]) 0))] + "!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)" + "mov{b}\t{%h1, %0|%0, %h1}" + [(set_attr "type" "imov") + (set_attr "mode" "QI")]) + (define_expand "extv" [(set (match_operand:SWI24 0 "register_operand") (sign_extract:SWI24 (match_operand:SWI24 1 "register_operand") @@ -6645,6 +6658,39 @@ (define_insn_and_split "*addqi_ext_1_slp" [(set_attr "type" "alu") (set_attr "mode" "QI")]) +(define_insn_and_split "*addqi_ext_2_slp" + [(set (strict_low_part (match_operand:QI 0 "register_operand" "+&Q")) + (plus:QI + (subreg:QI + (match_operator:SWI248 3 "extract_operator" + [(match_operand 1 "int248_register_operand" "Q") + (const_int 8) + (const_int 8)]) 0) + (subreg:QI + (match_operator:SWI248 4 "extract_operator" + [(match_operand 2 "int248_register_operand" "Q") + (const_int 8) + (const_int 8)]) 0))) + (clobber (reg:CC FLAGS_REG))] + "!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)" + "#" + "&& reload_completed" + [(set (strict_low_part (match_dup 0)) + (subreg:QI + (match_op_dup 4 + [(match_dup 2) (const_int 8) (const_int 8)]) 0)) + (parallel + [(set (strict_low_part (match_dup 0)) + (plus:QI + (subreg:QI + (match_op_dup 3 + [(match_dup 1) (const_int 8) (const_int 8)]) 0) + (match_dup 0))) + (clobber (reg:CC FLAGS_REG))])] + "" + [(set_attr "type" "alu") + (set_attr "mode" "QI")]) + ;; Split non destructive adds if we cannot use lea. (define_split [(set (match_operand:SWI48 0 "register_operand") @@ -7688,6 +7734,39 @@ (define_insn_and_split "*subqi_ext_1_slp" [(set_attr "type" "alu") (set_attr "mode" "QI")]) +(define_insn_and_split "*subqi_ext_2_slp" + [(set (strict_low_part (match_operand:QI 0 "register_operand" "+&Q")) + (minus:QI + (subreg:QI + (match_operator:SWI248 3 "extract_operator" + [(match_operand 1 "int248_register_operand" "Q") + (const_int 8) + (const_int 8)]) 0) + (subreg:QI + (match_operator:SWI248 4 "extract_operator" + [(match_operand 2 "int248_register_operand" "Q") + (const_int 8) + (const_int 8)]) 0))) + (clobber (reg:CC FLAGS_REG))] + "!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)" + "#" + "&& reload_completed" + [(set (strict_low_part (match_dup 0)) + (subreg:QI + (match_op_dup 3 + [(match_dup 1) (const_int 8) (const_int 8)]) 0)) + (parallel + [(set (strict_low_part (match_dup 0)) + (minus:QI + (match_dup 0) + (subreg:QI + (match_op_dup 4 + [(match_dup 2) (const_int 8) (const_int 8)]) 0))) + (clobber (reg:CC FLAGS_REG))])] + "" + [(set_attr "type" "alu") + (set_attr "mode" "QI")]) + (define_insn "*sub_2" [(set (reg FLAGS_REG) (compare @@ -11513,6 +11592,39 @@ (define_insn_and_split "*qi_ext_1_slp" [(set_attr "type" "alu") (set_attr "mode" "QI")]) +(define_insn_and_split "*qi_ext_2_slp" + [(set (strict_low_part (match_operand:QI 0 "register_operand" "+&Q")) + (any_logic:QI + (subreg:QI + (match_operator:SWI248 3 "extract_operator" + [(match_operand 1 "int248_register_operand" "Q") + (const_int 8) + (const_int 8)]) 0) + (subreg:QI + (match_operator:SWI248 4 "extract_operator" + [(match_operand 2 "int248_register_operand" "Q") + (const_int 8) + (const_int 8)]) 0))) + (clobber (reg:CC FLAGS_REG))] + "!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)" + "#" + "&& reload_completed" + [(set (strict_low_part (match_dup 0)) + (subreg:QI + (match_op_dup 4 + [(match_dup 2) (const_int 8) (const_int 8)]) 0)) + (parallel + [(set (strict_low_part (match_dup 0)) + (any_logic:QI + (subreg:QI + (match_op_dup 3 + [(match_dup 1) (const_int 8) (const_int 8)]) 0) + (match_dup 0))) + (clobber (reg:CC FLAGS_REG))])] + "" + [(set_attr "type" "alu") + (set_attr "mode" "QI")]) + (define_split [(set (match_operand:SWI248 0 "register_operand") (and:SWI248 (match_operand:SWI248 1 "nonimmediate_operand") diff --git a/gcc/testsuite/gcc.target/i386/pr78904-8.c b/gcc/testsuite/gcc.target/i386/pr78904-8.c new file mode 100644 index 00000000000..3ca1d424c7e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr78904-8.c @@ -0,0 +1,25 @@ +/* PR target/78904 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -masm=att" } */ +/* { dg-final { scan-assembler-not "movzbl" } } */ + +struct S1 +{ + unsigned char val; + unsigned char pad1; + unsigned short pad2; +}; + +struct S2 +{ + unsigned char pad1; + unsigned char val; + unsigned short pad2; +}; + +struct S1 test (struct S1 a, struct S2 b) +{ + a.val = b.val; + + return a; +} diff --git a/gcc/testsuite/gcc.target/i386/pr78904-8a.c b/gcc/testsuite/gcc.target/i386/pr78904-8a.c new file mode 100644 index 00000000000..fe484a79a39 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr78904-8a.c @@ -0,0 +1,23 @@ +/* PR target/78904 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -masm=att" } */ +/* { dg-final { scan-assembler-not "movzbl" } } */ + +struct S1 +{ + unsigned char val; + unsigned char pad1; +}; + +struct S2 +{ + unsigned char pad1; + unsigned char val; +}; + +struct S1 test (struct S1 a, struct S2 b) +{ + a.val = b.val; + + return a; +} diff --git a/gcc/testsuite/gcc.target/i386/pr78904-8b.c b/gcc/testsuite/gcc.target/i386/pr78904-8b.c new file mode 100644 index 00000000000..cfed7c18b09 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr78904-8b.c @@ -0,0 +1,27 @@ +/* PR target/78904 */ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -masm=att" } */ +/* { dg-final { scan-assembler-not "movzbl" } } */ + +struct S1 +{ + unsigned char val; + unsigned char pad1; + unsigned short pad2; + unsigned int pad3; +}; + +struct S2 +{ + unsigned char pad1; + unsigned char val; + unsigned short pad2; + unsigned int pad3; +}; + +struct S1 test (struct S1 a, struct S2 b) +{ + a.val = b.val; + + return a; +} diff --git a/gcc/testsuite/gcc.target/i386/pr78904-9.c b/gcc/testsuite/gcc.target/i386/pr78904-9.c new file mode 100644 index 00000000000..aa80be4c8b5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr78904-9.c @@ -0,0 +1,63 @@ +/* PR target/78904 */ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -masm=att" } */ +/* { dg-final { scan-assembler-not "movzbl" } } */ + +struct S1 +{ + unsigned char val; + unsigned char pad1; + unsigned short pad2; +}; + +struct S2 +{ + unsigned char pad1; + unsigned char val; + unsigned short pad2; +}; + +struct S1 test_and (struct S1 a, struct S2 b, struct S2 c) +{ + a.val = b.val & c.val; + + return a; +} + +/* { dg-final { scan-assembler "\[ \t\]andb" } } */ + +struct S1 test_or (struct S1 a, struct S2 b, struct S2 c) +{ + a.val = b.val | c.val; + + return a; +} + +/* { dg-final { scan-assembler "\[ \t\]orb" } } */ + +struct S1 test_xor (struct S1 a, struct S2 b, struct S2 c) +{ + a.val = b.val ^ c.val; + + return a; +} + +/* { dg-final { scan-assembler "\[ \t\]xorb" } } */ + +struct S1 test_add (struct S1 a, struct S2 b, struct S2 c) +{ + a.val = b.val + c.val; + + return a; +} + +/* { dg-final { scan-assembler "\[ \t\]addb" } } */ + +struct S1 test_sub (struct S1 a, struct S2 b, struct S2 c) +{ + a.val = b.val - c.val; + + return a; +} + +/* { dg-final { scan-assembler "\[ \t\]subb" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr78904-9a.c b/gcc/testsuite/gcc.target/i386/pr78904-9a.c new file mode 100644 index 00000000000..009ae241199 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr78904-9a.c @@ -0,0 +1,61 @@ +/* PR target/78904 */ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -masm=att" } */ +/* { dg-final { scan-assembler-not "movzbl" } } */ + +struct S1 +{ + unsigned char val; + unsigned char pad1; +}; + +struct S2 +{ + unsigned char pad1; + unsigned char val; +}; + +struct S1 test_and (struct S1 a, struct S2 b, struct S2 c) +{ + a.val = b.val & c.val; + + return a; +} + +/* { dg-final { scan-assembler "\[ \t\]andb" } } */ + +struct S1 test_or (struct S1 a, struct S2 b, struct S2 c) +{ + a.val = b.val | c.val; + + return a; +} + +/* { dg-final { scan-assembler "\[ \t\]orb" } } */ + +struct S1 test_xor (struct S1 a, struct S2 b, struct S2 c) +{ + a.val = b.val ^ c.val; + + return a; +} + +/* { dg-final { scan-assembler "\[ \t\]xorb" } } */ + +struct S1 test_add (struct S1 a, struct S2 b, struct S2 c) +{ + a.val = b.val + c.val; + + return a; +} + +/* { dg-final { scan-assembler "\[ \t\]addb" } } */ + +struct S1 test_sub (struct S1 a, struct S2 b, struct S2 c) +{ + a.val = b.val - c.val; + + return a; +} + +/* { dg-final { scan-assembler "\[ \t\]subb" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr78904-9b.c b/gcc/testsuite/gcc.target/i386/pr78904-9b.c new file mode 100644 index 00000000000..bf68f8bef20 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr78904-9b.c @@ -0,0 +1,65 @@ +/* PR target/78904 */ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -masm=att" } */ +/* { dg-final { scan-assembler-not "movzbl" } } */ + +struct S1 +{ + unsigned char val; + unsigned char pad1; + unsigned short pad2; + unsigned int pad3; +}; + +struct S2 +{ + unsigned char pad1; + unsigned char val; + unsigned short pad2; + unsigned int pad3; +}; + +struct S1 test_and (struct S1 a, struct S2 b, struct S2 c) +{ + a.val = b.val & c.val; + + return a; +} + +/* { dg-final { scan-assembler "\[ \t\]andb" } } */ + +struct S1 test_or (struct S1 a, struct S2 b, struct S2 c) +{ + a.val = b.val | c.val; + + return a; +} + +/* { dg-final { scan-assembler "\[ \t\]orb" } } */ + +struct S1 test_xor (struct S1 a, struct S2 b, struct S2 c) +{ + a.val = b.val ^ c.val; + + return a; +} + +/* { dg-final { scan-assembler "\[ \t\]xorb" } } */ + +struct S1 test_add (struct S1 a, struct S2 b, struct S2 c) +{ + a.val = b.val + c.val; + + return a; +} + +/* { dg-final { scan-assembler "\[ \t\]addb" } } */ + +struct S1 test_sub (struct S1 a, struct S2 b, struct S2 c) +{ + a.val = b.val - c.val; + + return a; +} + +/* { dg-final { scan-assembler "\[ \t\]subb" } } */