From patchwork Mon May 18 15:28:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 1292589 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=gcc.gnu.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=IKSs+h7X; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 49QjbB67YSz9sTD for ; Tue, 19 May 2020 01:28:38 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9E97938930D2; Mon, 18 May 2020 15:28:36 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 9E97938930D2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1589815716; bh=6WfskcWCz/J+VBTauJ6GXwNpEZeu96X8xglwaEJnwCg=; h=Date:Subject:To:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=IKSs+h7Xt3RHCsGJyfIT742PkzS4GDsLmGfKi3XVRO9OCQ64H3GkcggZ7JfEhLUsz 0iS7xAJoY/s3soCUffd62DgraWnngPFgTZrtnzdmFR6DuUNv2MPdbx6wFvCoZgp4WV ISWsFpGumOxCrvtd+Te8gM+rAQVhC3opndkjiKDw= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-io1-xd32.google.com (mail-io1-xd32.google.com [IPv6:2607:f8b0:4864:20::d32]) by sourceware.org (Postfix) with ESMTPS id 349A2388A832 for ; Mon, 18 May 2020 15:28:34 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 349A2388A832 Received: by mail-io1-xd32.google.com with SMTP id d7so10994865ioq.5 for ; Mon, 18 May 2020 08:28:34 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=6WfskcWCz/J+VBTauJ6GXwNpEZeu96X8xglwaEJnwCg=; b=nEBbfYmRg//Dl0uB3CljL7Sht4vSCH8Y+ZYHRnUE8QbeRLC0PJwHakp1+mcE9sAgBG MBZt33KWvPXj9sFxTaDhp81VKf5qGnjf3Jq47uq48XqEariSvQtPq6hv5gA/hCFJtJBm yTxvHxe6g1c7NruInCZWSbX9YPjns68GJ61fU4iykYisptDWact9vPdUUJa6arr6iJm2 M2zUZ+RUcumS4yQ+kA8B+xsnS9bQx+pYqAQSk1YebHDZHtQqtiGc3RfgwnlBaCPL9S3n AJBNVdaYwneEDd+PU2FY8E/cvJP1nz1aSfFEZzctheq9A/ApT3qQ1oGf4icwBTkg5uyH yowA== X-Gm-Message-State: AOAM531t5LUno5RakRpTaG9EB78qgb3+kk/Yoeye/XiYOCiZQjunpcVU x2cZl7siiJ7YRyluYWL4qOnDYcgeWm2wLEfiwfZ9fCI/QR8= X-Google-Smtp-Source: ABdhPJygyPxWNQ8U1+IrqpTR9WjfboKvPc65XQgoEtZI/PQAyjvTHdUgBIDLReXRyy+ElZKpXOcDBBfRm2J16NDbP4w= X-Received: by 2002:a02:93c8:: with SMTP id z66mr16378339jah.23.1589815713296; Mon, 18 May 2020 08:28:33 -0700 (PDT) MIME-Version: 1.0 Date: Mon, 18 May 2020 17:28:21 +0200 Message-ID: Subject: [committed] i386: Improve vector mode and TFmode ABS and NEG patterns To: "gcc-patches@gcc.gnu.org" X-Spam-Status: No, score=-10.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Uros Bizjak via Gcc-patches From: Uros Bizjak Reply-To: Uros Bizjak Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" gcc/ChangeLog: 2020-05-18 Uroš Bizjak * config/i386/i386-expand.c (ix86_expand_fp_absneg_operator): Do not emit FLAGS_REG clobber for TFmode. * config/i386/i386.md (*tf2_1): Rewrite as define_insn_and_split. Mark operands 1 and 2 commutative. (*nabstf2_1): Ditto. (absneg SSE splitter): Use MODEF mode iterator instead of SSEMODEF. Do not swap memory operands. Simplify RTX generation. (neg abs SSE splitter): Ditto. * config/i386/sse.md (*2): Mark operands 1 and 2 commutative. Do not swap operands. Simplify RTX generation. (*nabs2): Ditto. No functional changes. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Uros. diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c index 26531585c5f..2865cced66c 100644 --- a/gcc/config/i386/i386-expand.c +++ b/gcc/config/i386/i386-expand.c @@ -1716,9 +1716,7 @@ ix86_expand_fp_absneg_operator (enum rtx_code code, machine_mode mode, machine_mode vmode = mode; rtvec par; - if (vector_mode) - use_sse = true; - else if (mode == TFmode) + if (vector_mode || mode == TFmode) use_sse = true; else if (TARGET_SSE_MATH) { @@ -1743,7 +1741,7 @@ ix86_expand_fp_absneg_operator (enum rtx_code code, machine_mode mode, Create the appropriate mask now. */ mask = ix86_build_signbit_mask (vmode, vector_mode, code == ABS); use = gen_rtx_USE (VOIDmode, mask); - if (vector_mode) + if (vector_mode || mode == TFmode) par = gen_rtvec (2, set, use); else { diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 9fd32f28bf3..aa4f25b7065 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -10005,32 +10005,6 @@ [(set_attr "type" "negnot") (set_attr "mode" "")]) -(define_expand "tf2" - [(set (match_operand:TF 0 "register_operand") - (absneg:TF (match_operand:TF 1 "register_operand")))] - "TARGET_SSE" - "ix86_expand_fp_absneg_operator (, TFmode, operands); DONE;") - -(define_insn "*tf2_1" - [(set (match_operand:TF 0 "register_operand" "=x,x,Yv,Yv") - (absneg:TF - (match_operand:TF 1 "vector_operand" "0,xBm,Yv,m"))) - (use (match_operand:TF 2 "vector_operand" "xBm,0,Yvm,Yv")) - (clobber (reg:CC FLAGS_REG))] - "TARGET_SSE" - "#" - [(set_attr "isa" "noavx,noavx,avx,avx")]) - -(define_insn "*nabstf2_1" - [(set (match_operand:TF 0 "register_operand" "=x,x,Yv,Yv") - (neg:TF - (abs:TF - (match_operand:TF 1 "vector_operand" "0,xBm,Yv,m")))) - (use (match_operand:TF 2 "vector_operand" "xBm,0,Yvm,Yv"))] - "TARGET_SSE" - "#" - [(set_attr "isa" "noavx,noavx,avx,avx")]) - ;; Special expand pattern to handle integer mode abs (define_expand "abs2" @@ -10056,6 +10030,39 @@ DONE; }) +(define_expand "tf2" + [(set (match_operand:TF 0 "register_operand") + (absneg:TF (match_operand:TF 1 "register_operand")))] + "TARGET_SSE" + "ix86_expand_fp_absneg_operator (, TFmode, operands); DONE;") + +(define_insn_and_split "*tf2_1" + [(set (match_operand:TF 0 "register_operand" "=x,Yv") + (absneg:TF + (match_operand:TF 1 "vector_operand" "%0,Yv"))) + (use (match_operand:TF 2 "vector_operand" "xBm,Yvm"))] + "TARGET_SSE" + "#" + "&& reload_completed" + [(set (match_dup 0) + (:TF (match_dup 1) (match_dup 2)))] + "" + [(set_attr "isa" "noavx,avx")]) + +(define_insn_and_split "*nabstf2_1" + [(set (match_operand:TF 0 "register_operand" "=x,Yv") + (neg:TF + (abs:TF + (match_operand:TF 1 "vector_operand" "%0,Yv")))) + (use (match_operand:TF 2 "vector_operand" "xBm,Yvm"))] + "TARGET_SSE" + "#" + "&& reload_completed" + [(set (match_dup 0) + (ior:TF (match_dup 1) (match_dup 2)))] + "" + [(set_attr "isa" "noavx,avx")]) + (define_expand "2" [(set (match_operand:X87MODEF 0 "register_operand") (absneg:X87MODEF (match_operand:X87MODEF 1 "register_operand")))] @@ -10108,36 +10115,24 @@ (symbol_ref "false"))))]) (define_split - [(set (match_operand:SSEMODEF 0 "sse_reg_operand") - (absneg:SSEMODEF - (match_operand:SSEMODEF 1 "vector_operand"))) + [(set (match_operand:MODEF 0 "sse_reg_operand") + (absneg:MODEF + (match_operand:MODEF 1 "vector_operand"))) (use (match_operand: 2 "vector_operand")) (clobber (reg:CC FLAGS_REG))] - "((SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) - || (TARGET_SSE && (mode == TFmode))) + "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH && reload_completed" - [(set (match_dup 0) (match_dup 3))] + [(set (match_dup 0) + (: (match_dup 1) (match_dup 2)))] { machine_mode mode = mode; machine_mode vmode = mode; - enum rtx_code absneg_op = == ABS ? AND : XOR; operands[0] = lowpart_subreg (vmode, operands[0], mode); operands[1] = lowpart_subreg (vmode, operands[1], mode); - if (TARGET_AVX) - { - if (MEM_P (operands[1])) - std::swap (operands[1], operands[2]); - } - else - { - if (operands_match_p (operands[0], operands[2])) - std::swap (operands[1], operands[2]); - } - - operands[3] - = gen_rtx_fmt_ee (absneg_op, vmode, operands[1], operands[2]); + if (!TARGET_AVX && operands_match_p (operands[0], operands[2])) + std::swap (operands[1], operands[2]); }) (define_split @@ -10168,15 +10163,15 @@ [(set_attr "isa" "noavx,noavx,avx")]) (define_split - [(set (match_operand:SSEMODEF 0 "sse_reg_operand") - (neg:SSEMODEF - (abs:SSEMODEF - (match_operand:SSEMODEF 1 "vector_operand")))) + [(set (match_operand:MODEF 0 "sse_reg_operand") + (neg:MODEF + (abs:MODEF + (match_operand:MODEF 1 "vector_operand")))) (use (match_operand: 2 "vector_operand"))] - "((SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) - || (TARGET_SSE && (mode == TFmode))) + "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH && reload_completed" - [(set (match_dup 0) (match_dup 3))] + [(set (match_dup 0) + (ior: (match_dup 1) (match_dup 2)))] { machine_mode mode = mode; machine_mode vmode = mode; @@ -10184,19 +10179,8 @@ operands[0] = lowpart_subreg (vmode, operands[0], mode); operands[1] = lowpart_subreg (vmode, operands[1], mode); - if (TARGET_AVX) - { - if (MEM_P (operands[1])) - std::swap (operands[1], operands[2]); - } - else - { - if (operands_match_p (operands[0], operands[2])) - std::swap (operands[1], operands[2]); - } - - operands[3] - = gen_rtx_fmt_ee (IOR, vmode, operands[1], operands[2]); + if (!TARGET_AVX && operands_match_p (operands[0], operands[2])) + std::swap (operands[1], operands[2]); }) ;; Conditionalize these after reload. If they match before reload, we diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 28d2c434caf..153982c9f12 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -1638,59 +1638,31 @@ "ix86_expand_fp_absneg_operator (, mode, operands); DONE;") (define_insn_and_split "*2" - [(set (match_operand:VF 0 "register_operand" "=x,x,v,v") + [(set (match_operand:VF 0 "register_operand" "=x,v") (absneg:VF - (match_operand:VF 1 "vector_operand" "0, xBm,v, m"))) - (use (match_operand:VF 2 "vector_operand" "xBm,0, vm,v"))] + (match_operand:VF 1 "vector_operand" "%0,v"))) + (use (match_operand:VF 2 "vector_operand" "xBm,vm"))] "TARGET_SSE" "#" "&& reload_completed" - [(set (match_dup 0) (match_dup 3))] -{ - enum rtx_code absneg_op = == ABS ? AND : XOR; - - if (TARGET_AVX) - { - if (MEM_P (operands[1])) - std::swap (operands[1], operands[2]); - } - else - { - if (operands_match_p (operands[0], operands[2])) - std::swap (operands[1], operands[2]); - } - - operands[3] - = gen_rtx_fmt_ee (absneg_op, mode, operands[1], operands[2]); -} - [(set_attr "isa" "noavx,noavx,avx,avx")]) + [(set (match_dup 0) + (:VF (match_dup 1) (match_dup 2)))] + "" + [(set_attr "isa" "noavx,avx")]) (define_insn_and_split "*nabs2" - [(set (match_operand:VF 0 "register_operand" "=x,x,v,v") + [(set (match_operand:VF 0 "register_operand" "=x,v") (neg:VF (abs:VF - (match_operand:VF 1 "vector_operand" "0,xBm,v,m")))) - (use (match_operand:VF 2 "vector_operand" "xBm,0,vm,v"))] + (match_operand:VF 1 "vector_operand" "%0,v")))) + (use (match_operand:VF 2 "vector_operand" "xBm,vm"))] "TARGET_SSE" "#" "&& reload_completed" - [(set (match_dup 0) (match_dup 3))] -{ - if (TARGET_AVX) - { - if (MEM_P (operands[1])) - std::swap (operands[1], operands[2]); - } - else - { - if (operands_match_p (operands[0], operands[2])) - std::swap (operands[1], operands[2]); - } - - operands[3] - = gen_rtx_fmt_ee (IOR, mode, operands[1], operands[2]); -} - [(set_attr "isa" "noavx,noavx,avx,avx")]) + [(set (match_dup 0) + (ior:VF (match_dup 1) (match_dup 2)))] + "" + [(set_attr "isa" "noavx,avx")]) (define_expand "3" [(set (match_operand:VF 0 "register_operand")