From patchwork Thu Aug 29 18:18:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 1155461 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-507969-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="e/XYxSrb"; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="SGwYBs31"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46K9pf3pMfz9sR4 for ; Fri, 30 Aug 2019 04:18:32 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; q= dns; s=default; b=W4uRKlAhd6sEOqil3TVpqlUpskcPx12KgJttOX7b6t46vI 8cVJtsYwdVOFzqYYTni4QQ2gjm+WZRd1tc4B/8HBo+yBczE+7jcbn6zOJb3Kjr3G 8m6Az3AebY34xZ998Zs3Cz3ZS0FmzQt2Xs1MOFP9JkqtMFAgiRmhRwa4zU+mE= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; s= default; bh=w6QbOs2AYF7KZtm2JSuNHzdONVM=; b=e/XYxSrbcXDxbqlU3XLN SnLNdUwEc23MFtdsTOyn9xuuRAVuskbztbpMxsm63S+5XRA39O5Up2PynYskmQy6 zdQByQZruoHcle0JPkfDc1hxh8vMBiwUTrkJIyYGEdjcliRcp4YqhzkzPjAinOjJ TAWtRcoZbJa82yMukjvoJM4= Received: (qmail 107222 invoked by alias); 29 Aug 2019 18:18:25 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 107213 invoked by uid 89); 29 Aug 2019 18:18:25 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-15.3 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: mail-io1-f52.google.com Received: from mail-io1-f52.google.com (HELO mail-io1-f52.google.com) (209.85.166.52) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 29 Aug 2019 18:18:24 +0000 Received: by mail-io1-f52.google.com with SMTP id d25so6289840iob.6 for ; Thu, 29 Aug 2019 11:18:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:from:date:message-id:subject:to; bh=C0uX4v73Zi/Vyqlyk3Tmx5hZXe4lgZ8/TXZ1KEvW/Dw=; b=SGwYBs31AdvXBW8eWUpyed6lxrVUPF9njXs2vejRNhYZ9heLYp3QreT2W9GpNgftIO gGr5BYKJCOih7112Moqx1s72RU2Htd5SUSf/jPMFMDL2zpxxQ9CUrXXyd0C3N8Vp8Jdj 7Ibk/u3wxN26nCps0jVtI8dlcLoyp4r9MSmdZcQcf9tcg6ZZl0Up7Idsc57HbfuQeJ01 cAL1Ru+1dmu/blO1V4jqU+0GI9Mrkg9F1uk5c2FZybJhLq6max6c1ZyKvM8OIpOn87Ss PwOwfU0bnB1r0wjzmpcjfPXPGZotkJ/9AAKlW1qAN4ktu4xzvhxBdUGMmSnYGRMeKS9s EuJA== MIME-Version: 1.0 From: Uros Bizjak Date: Thu, 29 Aug 2019 20:18:11 +0200 Message-ID: Subject: [PATCH, i386]: Tighten inline_secondary_memory_needed to reject moves between (SSE, mask) and non-general regs To: "gcc-patches@gcc.gnu.org" 2019-08-29 Uroš Bizjak * config/i386/i386.c (inline_secondary_memory_needed): Return true for moves between SSE and non-general registers and between mask and non-general registers. (ix86_register_move_cost): Remove stalled comment. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Committed to mainline SVN. Uros. diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index d2d84eb11663..1c9c719f22a3 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -18306,32 +18306,36 @@ inline_secondary_memory_needed (machine_mode mode, reg_class_t class1, if (FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class2)) return true; - /* Between mask and general, we have moves no larger than word size. */ - if ((MASK_CLASS_P (class1) != MASK_CLASS_P (class2)) - && (GET_MODE_SIZE (mode) > UNITS_PER_WORD)) - return true; - /* ??? This is a lie. We do have moves between mmx/general, and for mmx/sse2. But by saying we need secondary memory we discourage the register allocator from using the mmx registers unless needed. */ if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2)) return true; + /* Between mask and general, we have moves no larger than word size. */ + if (MASK_CLASS_P (class1) != MASK_CLASS_P (class2)) + { + if (!(INTEGER_CLASS_P (class1) || INTEGER_CLASS_P (class2)) + || GET_MODE_SIZE (mode) > UNITS_PER_WORD) + return true; + } + if (SSE_CLASS_P (class1) != SSE_CLASS_P (class2)) { /* SSE1 doesn't have any direct moves from other classes. */ if (!TARGET_SSE2) return true; + /* Between SSE and general, we have moves no larger than word size. */ + if (!(INTEGER_CLASS_P (class1) || INTEGER_CLASS_P (class2)) + || GET_MODE_SIZE (mode) > UNITS_PER_WORD) + return true; + /* If the target says that inter-unit moves are more expensive than moving through memory, then don't generate them. */ if ((SSE_CLASS_P (class1) && !TARGET_INTER_UNIT_MOVES_FROM_VEC) || (SSE_CLASS_P (class2) && !TARGET_INTER_UNIT_MOVES_TO_VEC)) return true; - - /* Between SSE and general, we have moves no larger than word size. */ - if (GET_MODE_SIZE (mode) > UNITS_PER_WORD) - return true; } return false; @@ -18608,15 +18612,7 @@ ix86_register_move_cost (machine_mode mode, reg_class_t class1_i, if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2)) gcc_unreachable (); - /* Moves between SSE and integer units are expensive. */ if (SSE_CLASS_P (class1) != SSE_CLASS_P (class2)) - - /* ??? By keeping returned value relatively high, we limit the number - of moves between integer and SSE registers for all targets. - Additionally, high value prevents problem with x86_modes_tieable_p(), - where integer modes in SSE registers are not tieable - because of missing QImode and HImode moves to, from or between - MMX/SSE registers. */ return (SSE_CLASS_P (class1) ? ix86_cost->hard_register.sse_to_integer : ix86_cost->hard_register.integer_to_sse);