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[committed] i386: Force operand 1 of bswapsi2 to a register for !TARGET_BSWAP [PR115321]

Message ID CAFULd4Yq89_wAprZa7EtiAyRo098NucVbyiKo_xO1buWZepDhQ@mail.gmail.com
State New
Headers show
Series [committed] i386: Force operand 1 of bswapsi2 to a register for !TARGET_BSWAP [PR115321] | expand

Commit Message

Uros Bizjak June 3, 2024, 1:51 p.m. UTC 
PR target/115321

gcc/ChangeLog:

    * config/i386/i386.md (bswapsi2): Force operand 1
    to a register also for !TARGET_BSWAP.

gcc/testsuite/ChangeLog:

    * gcc.target/i386/pr115321.c: New test.

Bootstrapped and regression tested on x86_64-linux-gnu {,m32}.

Uros.
diff mbox series

Patch

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 2c95395b7be..ef83984d00e 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -21193,18 +21193,19 @@  (define_expand "bswapsi2"
 	(bswap:SI (match_operand:SI 1 "nonimmediate_operand")))]
   ""
 {
-  if (TARGET_MOVBE)
-    ;
-  else if (TARGET_BSWAP)
-    operands[1] = force_reg (SImode, operands[1]);
-  else
+  if (!TARGET_MOVBE)
     {
-      rtx x = gen_reg_rtx (SImode);
+      operands[1] = force_reg (SImode, operands[1]);
 
-      emit_insn (gen_bswaphisi2_lowpart (x, operands[1]));
-      emit_insn (gen_rotlsi3 (x, x, GEN_INT (16)));
-      emit_insn (gen_bswaphisi2_lowpart (operands[0], x));
-      DONE;
+      if (!TARGET_BSWAP)
+	{
+	  rtx x = gen_reg_rtx (SImode);
+
+	  emit_insn (gen_bswaphisi2_lowpart (x, operands[1]));
+	  emit_insn (gen_rotlsi3 (x, x, GEN_INT (16)));
+	  emit_insn (gen_bswaphisi2_lowpart (operands[0], x));
+	  DONE;
+	}
     }
 })
 
diff --git a/gcc/testsuite/gcc.target/i386/pr115321.c b/gcc/testsuite/gcc.target/i386/pr115321.c
new file mode 100644
index 00000000000..0ddab9bd7a5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr115321.c
@@ -0,0 +1,4 @@ 
+/* { dg-do compile { target ia32 } } */
+/* { dg-options "-march=i386" } */
+
+unsigned foo (unsigned x) { return __builtin_bswap32 (x); }