@@ -14617,6 +14617,11 @@ ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt)
switch (mode)
{
case E_V2SImode:
+ use_vec_extr = TARGET_MMX_WITH_SSE && TARGET_SSE4_1;
+ if (use_vec_extr)
+ break;
+ /* FALLTHRU */
+
case E_V2SFmode:
if (!mmx_ok)
break;
@@ -14866,7 +14871,10 @@ ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt)
return;
case E_V8QImode:
+ use_vec_extr = TARGET_MMX_WITH_SSE && TARGET_SSE4_1;
/* ??? Could extract the appropriate HImode element and shift. */
+ break;
+
default:
break;
}
@@ -1510,23 +1510,73 @@
(set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
-(define_insn "mmx_pextrw"
- [(set (match_operand:SI 0 "register_operand" "=r,r")
- (zero_extend:SI
+(define_insn "*mmx_pextrw"
+ [(set (match_operand:HI 0 "register_sse4nonimm_operand" "=r,r,m")
+ (vec_select:HI
+ (match_operand:V4HI 1 "register_operand" "y,Yv,Yv")
+ (parallel [(match_operand:SI 2 "const_0_to_3_operand" "n,n,n")])))]
+ "(TARGET_MMX || TARGET_MMX_WITH_SSE)
+ && (TARGET_SSE || TARGET_3DNOW_A)"
+ "@
+ pextrw\t{%2, %1, %k0|%k0, %1, %2}
+ %vpextrw\t{%2, %1, %k0|%k0, %1, %2}
+ %vpextrw\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "*,sse2,sse4")
+ (set_attr "mmx_isa" "native,*,*")
+ (set_attr "type" "mmxcvt,sselog1,sselog1")
+ (set_attr "length_immediate" "1")
+ (set_attr "prefix" "orig,maybe_vex,maybe_vex")
+ (set_attr "mode" "DI,TI,TI")])
+
+(define_insn "*mmx_pextrw_zext"
+ [(set (match_operand:SWI48 0 "register_operand" "=r,r")
+ (zero_extend:SWI48
(vec_select:HI
(match_operand:V4HI 1 "register_operand" "y,Yv")
(parallel [(match_operand:SI 2 "const_0_to_3_operand" "n,n")]))))]
"(TARGET_MMX || TARGET_MMX_WITH_SSE)
&& (TARGET_SSE || TARGET_3DNOW_A)"
"@
- pextrw\t{%2, %1, %0|%0, %1, %2}
- %vpextrw\t{%2, %1, %0|%0, %1, %2}"
+ pextrw\t{%2, %1, %k0|%k0, %1, %2}
+ %vpextrw\t{%2, %1, %k0|%k0, %1, %2}"
[(set_attr "isa" "*,sse2")
(set_attr "mmx_isa" "native,*")
(set_attr "type" "mmxcvt,sselog1")
(set_attr "length_immediate" "1")
+ (set_attr "prefix" "orig,maybe_vex")
(set_attr "mode" "DI,TI")])
+(define_insn "*mmx_pextrb"
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=r,m")
+ (vec_select:QI
+ (match_operand:V8QI 1 "register_operand" "Yv,Yv")
+ (parallel [(match_operand:SI 2 "const_0_to_7_operand" "n,n")])))]
+ "TARGET_MMX_WITH_SSE && TARGET_SSE4_1"
+ "@
+ %vpextrb\t{%2, %1, %k0|%k0, %1, %2}
+ %vpextrb\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "type" "sselog1")
+ (set_attr "prefix_data16" "1")
+ (set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
+ (set_attr "prefix" "maybe_vex")
+ (set_attr "mode" "TI")])
+
+(define_insn "*mmx_pextrb_zext"
+ [(set (match_operand:SWI248 0 "register_operand" "=r")
+ (zero_extend:SWI248
+ (vec_select:QI
+ (match_operand:V8QI 1 "register_operand" "Yv")
+ (parallel [(match_operand:SI 2 "const_0_to_7_operand" "n")]))))]
+ "TARGET_MMX_WITH_SSE && TARGET_SSE4_1"
+ "%vpextrb\t{%2, %1, %k0|%k0, %1, %2}"
+ [(set_attr "type" "sselog1")
+ (set_attr "prefix_data16" "1")
+ (set_attr "prefix_extra" "1")
+ (set_attr "length_immediate" "1")
+ (set_attr "prefix" "maybe_vex")
+ (set_attr "mode" "TI")])
+
(define_expand "mmx_pshufw"
[(match_operand:V4HI 0 "register_operand")
(match_operand:V4HI 1 "register_mmxmem_operand")
We can implement these for TARGET_MMX_WITH_SSE (and TARGET_SSE4_1 in case of.pextrb). 2019-08-13 Uroš Bizjak <ubizjak@gmail.com> * config/i386/i386.md (ix86_expand_vector_extract) <case E_V2SImode>: Use vec_extr path for TARGET_MMX_WITH_SSE && TARGET_SSE4_1. <case E_V8QImode>: Ditto. * config/i386/mmx.md (*mmx_pextrw_zext): Rename from mmx_pextrw. Use SWI48 mode iterator. Use %k to output operand 0. (*mmx_pextrw): New insn pattern. (*mmx_pextrb): Ditto. (*mmx_pextrb_zext): Ditto. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Committed to mainline SVN. Uros.