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[committed] i386: Add V2SFmode copysign, xorsign and signbit expanders [PR95046]

Message ID CAFULd4YgRhbAk=Y9xHdQREn7SjJqY=v3Fpd1tBZ71iEZWnec1w@mail.gmail.com
State New
Headers show
Series [committed] i386: Add V2SFmode copysign, xorsign and signbit expanders [PR95046] | expand

Commit Message

Uros Bizjak May 12, 2020, 5:28 p.m. UTC 
gcc/ChangeLog:

2020-05-12  Uroš Bizjak  <ubizjak@gmail.com>

    PR target/95046
    * config/i386/mmx.md (copysignv2sf3): New expander.
    (xorsignv2sf3): Ditto.
    (signbitv2sf3): Ditto.

testsuite/ChangeLog:

2020-05-12  Uroš Bizjak  <ubizjak@gmail.com>

    PR target/95046
    * gcc.target/i386/pr95046-4.c: New test.

Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.

Uros.
diff mbox series

Patch

diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index f6f302eb7ff..d159134e0fb 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -660,6 +660,47 @@ 
    (set_attr "prefix" "orig,vex")
    (set_attr "mode" "V4SF")])
 
+(define_expand "copysignv2sf3"
+  [(set (match_dup 4)
+	(and:V2SF
+	  (not:V2SF (match_dup 3))
+	  (match_operand:V2SF 1 "register_operand")))
+   (set (match_dup 5)
+	(and:V2SF (match_dup 3)
+		  (match_operand:V2SF 2 "register_operand")))
+   (set (match_operand:V2SF 0 "register_operand")
+	(ior:V2SF (match_dup 4) (match_dup 5)))]
+  "TARGET_MMX_WITH_SSE"
+{
+  operands[3] = ix86_build_signbit_mask (V2SFmode, true, false);
+
+  operands[4] = gen_reg_rtx (V2SFmode);
+  operands[5] = gen_reg_rtx (V2SFmode);
+})
+
+(define_expand "xorsignv2sf3"
+  [(set (match_dup 4)
+	(and:V2SF (match_dup 3)
+		  (match_operand:V2SF 2 "register_operand")))
+   (set (match_operand:V2SF 0 "register_operand")
+	(xor:V2SF (match_dup 4)
+		  (match_operand:V2SF 1 "register_operand")))]
+  "TARGET_MMX_WITH_SSE"
+{
+  operands[3] = ix86_build_signbit_mask (V2SFmode, true, false);
+
+  operands[4] = gen_reg_rtx (V2SFmode);
+})
+
+(define_expand "signbitv2sf2"
+  [(set (match_operand:V2SI 0 "register_operand")
+	(lshiftrt:V2SI
+	  (subreg:V2SI
+	    (match_operand:V2SF 1 "register_operand") 0)
+	  (match_dup 2)))]
+  "TARGET_MMX_WITH_SSE"
+  "operands[2] = GEN_INT (GET_MODE_UNIT_BITSIZE (V2SFmode)-1);")
+
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;;
 ;; Parallel single-precision FMA multiply/accumulate instructions.
diff --git a/gcc/testsuite/gcc.target/i386/pr95046-4.c b/gcc/testsuite/gcc.target/i386/pr95046-4.c
new file mode 100644
index 00000000000..5a85045b095
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr95046-4.c
@@ -0,0 +1,39 @@ 
+/* PR target/95046 */
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O3 -msse2" } */
+
+
+float r[2], a[2], b[2];
+
+float copysignf (float, float);
+
+void
+test_copysign (void)
+{
+  for (int i = 0; i < 2; i++)
+    r[i] = copysignf (a[i], b[i]);
+}
+
+/* { dg-final { scan-assembler "\tv?andnps" } } */
+
+void
+test_xorsign (void)
+{
+  for (int i = 0; i < 2; i++)
+    r[i] = a[i] * copysignf (1.0f, b[i]);
+}
+
+/* { dg-final { scan-assembler "\tv?xorps" } } */
+
+int s[2];
+
+int signbitf (float);
+
+void
+test_signbitf (void)
+{
+  for (int i = 0; i < 2; i++)
+    s[i] = signbitf (a[i]);
+}
+
+/* { dg-final { scan-assembler "\tv?psrld" } } */