@@ -8436,6 +8436,14 @@ (define_expand "usubv<mode>4"
"ix86_fixup_binary_operands_no_copy (MINUS, <MODE>mode, operands,
TARGET_APX_NDD);")
+(define_expand "sub<mode>_3"
+ [(parallel [(set (reg:CC FLAGS_REG)
+ (compare:CC
+ (match_operand:SWI 1 "nonimmediate_operand")
+ (match_operand:SWI 2 "<general_operand>")))
+ (set (match_operand:SWI 0 "register_operand")
+ (minus:SWI (match_dup 1) (match_dup 2)))])])
+
(define_insn "*sub<mode>_3"
[(set (reg FLAGS_REG)
(compare (match_operand:SWI 1 "nonimmediate_operand" "0,0,rm,r")
@@ -9883,7 +9891,28 @@ (define_expand "usadd<mode>3"
emit_insn (gen_add<mode>3_cc_overflow_1 (res, operands[1], operands[2]));
emit_insn (gen_x86_mov<mode>cc_0_m1_neg (msk));
dst = expand_simple_binop (<MODE>mode, IOR, res, msk,
- operands[0], 1, OPTAB_DIRECT);
+ operands[0], 1, OPTAB_WIDEN);
+
+ if (!rtx_equal_p (dst, operands[0]))
+ emit_move_insn (operands[0], dst);
+ DONE;
+})
+
+(define_expand "ussub<mode>3"
+ [(set (match_operand:SWI 0 "register_operand")
+ (us_minus:SWI (match_operand:SWI 1 "register_operand")
+ (match_operand:SWI 2 "<general_operand>")))]
+ ""
+{
+ rtx res = gen_reg_rtx (<MODE>mode);
+ rtx msk = gen_reg_rtx (<MODE>mode);
+ rtx dst;
+
+ emit_insn (gen_sub<mode>_3 (res, operands[1], operands[2]));
+ emit_insn (gen_x86_mov<mode>cc_0_m1_neg (msk));
+ msk = expand_simple_unop (<MODE>mode, NOT, msk, NULL, 1);
+ dst = expand_simple_binop (<MODE>mode, AND, res, msk,
+ operands[0], 1, OPTAB_WIDEN);
if (!rtx_equal_p (dst, operands[0]))
emit_move_insn (operands[0], dst);