From patchwork Wed Jul 17 18:34:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 1133389 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-505217-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="SnWr6O0b"; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="vMEeOXRU"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45pmCf1CvCz9s3l for ; Thu, 18 Jul 2019 04:35:08 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; q= dns; s=default; b=hwD39w10zUphSmcQSzlo3/KvFZoGn6m1LGs4KI0g0hTlZ7 KZoZcoCO7FHyjiFuOYWeY3NZ/5D4ejnu6RFL3NbSIdg5kH+Ybh0w4OvFC5rS1YHF LoRHOMj0+cGTcnVpsQiIiPl+QtRWZ6AIYAM35UZ0xtceLXS1c5PCENTR6FDcI= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; s= default; bh=MAsBUaWwwU89SIFcBhbRZ4WH9us=; b=SnWr6O0btZz2x4HwkKXI 9RQPCXnsL7CumDTJqj0n/6R9YbBQZly/blWYGKA6u5miDnzsVntocOzqseqJ7FOh IMP7lhMmop3CxLUcMBWhlrZQYHMdi0MzRawDrjNc8to7wwUhZLOb6UJdjYHbx5co ORWSszmJDC+i9NR2UTI+Tx4= Received: (qmail 53993 invoked by alias); 17 Jul 2019 18:34:59 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 53985 invoked by uid 89); 17 Jul 2019 18:34:59 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-15.0 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.1 spammy=qm, CCC, m0 X-HELO: mail-ed1-f44.google.com Received: from mail-ed1-f44.google.com (HELO mail-ed1-f44.google.com) (209.85.208.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 17 Jul 2019 18:34:56 +0000 Received: by mail-ed1-f44.google.com with SMTP id e3so27045169edr.10 for ; Wed, 17 Jul 2019 11:34:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:from:date:message-id:subject:to; bh=iHOp7C8iqts95xmpSFyhBr27LsxZdBU514DFCThFMys=; b=vMEeOXRUqnDStamklKrNGDDIT4IzGSAtJM6/l0f0jJoDM8hm4lmBV8St3ctj3/oJ2n /wP7//lVxRa6e1SfbKFqSIp8i19+/xOcKzi3zl1E3BSAulzN+ntDuwYm6XXptRSfHWhk gkF6XSiBcD5OQzjB2YeIP5fZyCjdtqymWR7OwjJKEGU9cF40Z7twHbjKNJqo8rbrXFqS osvVAPpm9Mx8Wvxp9Pw10Dar8lxcK8NSc38ILc7woOFBA/H7YSpNIx5FxN0zoNUFfJoy yE9eF31ycUk3LoGZriVyunOl2wkqDyKL9+vUmzrkBQEwetEuAYCgtAASGfBjO7GT2sdB Td4g== MIME-Version: 1.0 From: Uros Bizjak Date: Wed, 17 Jul 2019 20:34:43 +0200 Message-ID: Subject: [PATCH, i386]: Remove redundant constraints from ALU insn patterns To: "gcc-patches@gcc.gnu.org" No functional changes. 2019-07-17 Uroš Bizjak * config/i386/i386.md (*add3_doubleword): Remove redundant constraints. (*add_1): Ditto. (*addhi_1): Ditto. (*addqi_1): Ditto. (*addqi_1_slp): Ditto. (*add_2): Ditto. (*addv4): Ditto. (*sub3_doubleword): Ditto. (*sub_1): Ditto. (*subqi_1_slp): Ditto. (*sub_2): Ditto. (*subv4): Ditto. (*sub_3): Ditto. (@add3_carry): Ditto. (@sub3_carry): Ditto. (*add3_cc_overflow_1): Ditto. (*add3_zext_cc_overflow_2): Ditto. (*anddi_1): Ditto. (*and_1): Ditto. (*andqi_1): Ditto. (*andqi_1_slp): Ditto. (*anddi_2): Ditto. (*andqi_2_maybe_si): Ditto. (*and_2): Ditto. (*andqi_2_slp): Ditto. (*_1): Ditto. (*qi_1): Ditto. (*qi_1_slp): Ditto. (*_2): Ditto. (*qi_2_slp): Ditto. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Committed to mainline SVN. Uros. diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index eb32d7c1d2a5..4a359e8035fd 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -5337,11 +5337,10 @@ "ix86_expand_binary_operator (PLUS, mode, operands); DONE;") (define_insn_and_split "*add3_doubleword" - [(set (match_operand: 0 "nonimmediate_operand" "=r,o") + [(set (match_operand: 0 "nonimmediate_operand" "=ro,r") (plus: (match_operand: 1 "nonimmediate_operand" "%0,0") - (match_operand: 2 "x86_64_hilo_general_operand" - "ro,r"))) + (match_operand: 2 "x86_64_hilo_general_operand" "r,o"))) (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (PLUS, mode, operands)" "#" @@ -5369,10 +5368,10 @@ }) (define_insn "*add_1" - [(set (match_operand:SWI48 0 "nonimmediate_operand" "=r,rm,r,r") + [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm,r,r,r") (plus:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "%0,0,r,r") - (match_operand:SWI48 2 "x86_64_general_operand" "rme,re,0,le"))) + (match_operand:SWI48 2 "x86_64_general_operand" "re,m,0,le"))) (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (PLUS, mode, operands)" { @@ -5475,7 +5474,7 @@ (define_insn "*addhi_1" [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r,Yp") (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,r,Yp") - (match_operand:HI 2 "general_operand" "rn,rm,0,ln"))) + (match_operand:HI 2 "general_operand" "rn,m,0,ln"))) (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (PLUS, HImode, operands)" { @@ -5524,7 +5523,7 @@ (define_insn "*addqi_1" [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,q,r,r,Yp") (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,q,0,r,Yp") - (match_operand:QI 2 "general_operand" "qn,qm,0,rn,0,ln"))) + (match_operand:QI 2 "general_operand" "qn,m,0,rn,0,ln"))) (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (PLUS, QImode, operands)" { @@ -5587,7 +5586,7 @@ (define_insn "*addqi_1_slp" [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q")) (plus:QI (match_dup 0) - (match_operand:QI 1 "general_operand" "qn,qm"))) + (match_operand:QI 1 "general_operand" "qn,m"))) (clobber (reg:CC FLAGS_REG))] "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)) && !(MEM_P (operands[0]) && MEM_P (operands[1]))" @@ -5680,9 +5679,9 @@ (compare (plus:SWI (match_operand:SWI 1 "nonimmediate_operand" "%0,0,") - (match_operand:SWI 2 "" ",,0")) + (match_operand:SWI 2 "" ",m,0")) (const_int 0))) - (set (match_operand:SWI 0 "nonimmediate_operand" "=,m,") + (set (match_operand:SWI 0 "nonimmediate_operand" "=m,,") (plus:SWI (match_dup 1) (match_dup 2)))] "ix86_match_ccmode (insn, CCGOCmode) && ix86_binary_operator_ok (PLUS, mode, operands)" @@ -6073,11 +6072,10 @@ (sign_extend: (match_operand:SWI 1 "nonimmediate_operand" "%0,0")) (sign_extend: - (match_operand:SWI 2 "" - "mWe,We"))) + (match_operand:SWI 2 "" "We,m"))) (sign_extend: (plus:SWI (match_dup 1) (match_dup 2))))) - (set (match_operand:SWI 0 "nonimmediate_operand" "=,m") + (set (match_operand:SWI 0 "nonimmediate_operand" "=m,") (plus:SWI (match_dup 1) (match_dup 2)))] "ix86_binary_operator_ok (PLUS, mode, operands)" "add{}\t{%2, %0|%0, %2}" @@ -6091,9 +6089,9 @@ (match_operand:SWI 1 "nonimmediate_operand" "0")) (match_operand: 3 "const_int_operand" "i")) (sign_extend: - (plus:SWI (match_dup 1) - (match_operand:SWI 2 "x86_64_immediate_operand" - ""))))) + (plus:SWI + (match_dup 1) + (match_operand:SWI 2 "x86_64_immediate_operand" ""))))) (set (match_operand:SWI 0 "nonimmediate_operand" "=m") (plus:SWI (match_dup 1) (match_dup 2)))] "ix86_binary_operator_ok (PLUS, mode, operands) @@ -6297,11 +6295,10 @@ "ix86_expand_binary_operator (MINUS, mode, operands); DONE;") (define_insn_and_split "*sub3_doubleword" - [(set (match_operand: 0 "nonimmediate_operand" "=r,o") + [(set (match_operand: 0 "nonimmediate_operand" "=ro,r") (minus: (match_operand: 1 "nonimmediate_operand" "0,0") - (match_operand: 2 "x86_64_hilo_general_operand" - "ro,r"))) + (match_operand: 2 "x86_64_hilo_general_operand" "r,o"))) (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (MINUS, mode, operands)" "#" @@ -6330,7 +6327,7 @@ [(set (match_operand:SWI 0 "nonimmediate_operand" "=m,") (minus:SWI (match_operand:SWI 1 "nonimmediate_operand" "0,0") - (match_operand:SWI 2 "" ",m"))) + (match_operand:SWI 2 "" ",m"))) (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (MINUS, mode, operands)" "sub{}\t{%2, %0|%0, %2}" @@ -6351,7 +6348,7 @@ (define_insn "*subqi_1_slp" [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q")) (minus:QI (match_dup 0) - (match_operand:QI 1 "general_operand" "qn,qm"))) + (match_operand:QI 1 "general_operand" "qn,m"))) (clobber (reg:CC FLAGS_REG))] "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)) && !(MEM_P (operands[0]) && MEM_P (operands[1]))" @@ -6364,7 +6361,7 @@ (compare (minus:SWI (match_operand:SWI 1 "nonimmediate_operand" "0,0") - (match_operand:SWI 2 "" ",m")) + (match_operand:SWI 2 "" ",m")) (const_int 0))) (set (match_operand:SWI 0 "nonimmediate_operand" "=m,") (minus:SWI (match_dup 1) (match_dup 2)))] @@ -6422,8 +6419,7 @@ (sign_extend: (match_operand:SWI 1 "nonimmediate_operand" "0,0")) (sign_extend: - (match_operand:SWI 2 "" - "We,m"))) + (match_operand:SWI 2 "" "We,m"))) (sign_extend: (minus:SWI (match_dup 1) (match_dup 2))))) (set (match_operand:SWI 0 "nonimmediate_operand" "=m,") @@ -6440,9 +6436,9 @@ (match_operand:SWI 1 "nonimmediate_operand" "0")) (match_operand: 3 "const_int_operand" "i")) (sign_extend: - (minus:SWI (match_dup 1) - (match_operand:SWI 2 "x86_64_immediate_operand" - ""))))) + (minus:SWI + (match_dup 1) + (match_operand:SWI 2 "x86_64_immediate_operand" ""))))) (set (match_operand:SWI 0 "nonimmediate_operand" "=m") (minus:SWI (match_dup 1) (match_dup 2)))] "ix86_binary_operator_ok (MINUS, mode, operands) @@ -6475,7 +6471,7 @@ (define_insn "*sub_3" [(set (reg FLAGS_REG) (compare (match_operand:SWI 1 "nonimmediate_operand" "0,0") - (match_operand:SWI 2 "" ",m"))) + (match_operand:SWI 2 "" ",m"))) (set (match_operand:SWI 0 "nonimmediate_operand" "=m,") (minus:SWI (match_dup 1) (match_dup 2)))] "ix86_match_ccmode (insn, CCmode) @@ -6518,7 +6514,7 @@ (match_operator:SWI 4 "ix86_carry_flag_operator" [(match_operand 3 "flags_reg_operand") (const_int 0)]) (match_operand:SWI 1 "nonimmediate_operand" "%0,0")) - (match_operand:SWI 2 "" ",m"))) + (match_operand:SWI 2 "" ",m"))) (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (PLUS, mode, operands)" "adc{}\t{%2, %0|%0, %2}" @@ -6618,7 +6614,7 @@ (match_operand:SWI 1 "nonimmediate_operand" "0,0") (match_operator:SWI 4 "ix86_carry_flag_operator" [(match_operand 3 "flags_reg_operand") (const_int 0)])) - (match_operand:SWI 2 "" ",m"))) + (match_operand:SWI 2 "" ",m"))) (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (MINUS, mode, operands)" "sbb{}\t{%2, %0|%0, %2}" @@ -6783,7 +6779,7 @@ (compare:CCC (plus:SWI (match_operand:SWI 1 "nonimmediate_operand" "%0,0") - (match_operand:SWI 2 "" ",m")) + (match_operand:SWI 2 "" ",m")) (match_dup 1))) (set (match_operand:SWI 0 "nonimmediate_operand" "=m,") (plus:SWI (match_dup 1) (match_dup 2)))] @@ -6824,7 +6820,7 @@ (compare:CCC (plus:SWI (match_operand:SWI 1 "nonimmediate_operand" "%0,0") - (match_operand:SWI 2 "" ",m")) + (match_operand:SWI 2 "" ",m")) (match_dup 2))) (set (match_operand:SWI 0 "nonimmediate_operand" "=m,") (plus:SWI (match_dup 1) (match_dup 2)))] @@ -8431,7 +8427,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r,r") (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,qm") - (match_operand:DI 2 "x86_64_szext_general_operand" "Z,re,rm,L"))) + (match_operand:DI 2 "x86_64_szext_general_operand" "Z,re,m,L"))) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && ix86_binary_operator_ok (AND, DImode, operands)" "@ @@ -8516,7 +8512,7 @@ (define_insn "*and_1" [(set (match_operand:SWI24 0 "nonimmediate_operand" "=rm,r,Ya") (and:SWI24 (match_operand:SWI24 1 "nonimmediate_operand" "%0,0,qm") - (match_operand:SWI24 2 "" "r,rm,L"))) + (match_operand:SWI24 2 "" "r,m,L"))) (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (AND, mode, operands)" "@ @@ -8537,7 +8533,7 @@ (define_insn "*andqi_1" [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r") (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") - (match_operand:QI 2 "general_operand" "qn,qmn,rn"))) + (match_operand:QI 2 "general_operand" "qn,m,rn"))) (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (AND, QImode, operands)" "@ @@ -8555,7 +8551,7 @@ (define_insn "*andqi_1_slp" [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q")) (and:QI (match_dup 0) - (match_operand:QI 1 "general_operand" "qn,qmn"))) + (match_operand:QI 1 "general_operand" "qn,m"))) (clobber (reg:CC FLAGS_REG))] "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)) && !(MEM_P (operands[0]) && MEM_P (operands[1]))" @@ -8644,9 +8640,9 @@ (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0") - (match_operand:DI 2 "x86_64_szext_general_operand" "Z,rem,re")) + (match_operand:DI 2 "x86_64_szext_general_operand" "Z,re,m")) (const_int 0))) - (set (match_operand:DI 0 "nonimmediate_operand" "=r,r,rm") + (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r") (and:DI (match_dup 1) (match_dup 2)))] "TARGET_64BIT && ix86_match_ccmode @@ -8687,9 +8683,9 @@ [(set (reg FLAGS_REG) (compare (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") - (match_operand:QI 2 "general_operand" "qmn,qn,n")) + (match_operand:QI 2 "general_operand" "qn,m,n")) (const_int 0))) - (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm,*r") + (set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,*r") (and:QI (match_dup 1) (match_dup 2)))] "ix86_binary_operator_ok (AND, QImode, operands) && ix86_match_ccmode (insn, @@ -8711,9 +8707,9 @@ [(set (reg FLAGS_REG) (compare (and:SWI124 (match_operand:SWI124 1 "nonimmediate_operand" "%0,0") - (match_operand:SWI124 2 "" ",")) + (match_operand:SWI124 2 "" ",m")) (const_int 0))) - (set (match_operand:SWI124 0 "nonimmediate_operand" "=,m") + (set (match_operand:SWI124 0 "nonimmediate_operand" "=m,") (and:SWI124 (match_dup 1) (match_dup 2)))] "ix86_match_ccmode (insn, CCNOmode) && ix86_binary_operator_ok (AND, mode, operands)" @@ -8723,9 +8719,8 @@ (define_insn "*andqi_2_slp" [(set (reg FLAGS_REG) - (compare (and:QI - (match_operand:QI 0 "nonimmediate_operand" "+q,qm") - (match_operand:QI 1 "nonimmediate_operand" "qmn,qn")) + (compare (and:QI (match_operand:QI 0 "nonimmediate_operand" "+qm,q") + (match_operand:QI 1 "nonimmediate_operand" "qn,m")) (const_int 0))) (set (strict_low_part (match_dup 0)) (and:QI (match_dup 0) (match_dup 1)))] @@ -9001,10 +8996,10 @@ }) (define_insn "*_1" - [(set (match_operand:SWI248 0 "nonimmediate_operand" "=r,rm") + [(set (match_operand:SWI248 0 "nonimmediate_operand" "=rm,r") (any_or:SWI248 (match_operand:SWI248 1 "nonimmediate_operand" "%0,0") - (match_operand:SWI248 2 "" ",r"))) + (match_operand:SWI248 2 "" "r,m"))) (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (, mode, operands)" "{}\t{%2, %0|%0, %2}" @@ -9081,9 +9076,9 @@ (set_attr "mode" "SI")]) (define_insn "*qi_1" - [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r") + [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r") (any_or:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") - (match_operand:QI 2 "general_operand" "qmn,qn,rn"))) + (match_operand:QI 2 "general_operand" "qn,m,rn"))) (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (, QImode, operands)" "@ @@ -9099,9 +9094,9 @@ (symbol_ref "true")))]) (define_insn "*qi_1_slp" - [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+q,m")) + [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q")) (any_or:QI (match_dup 0) - (match_operand:QI 1 "general_operand" "qmn,qn"))) + (match_operand:QI 1 "general_operand" "qn,m"))) (clobber (reg:CC FLAGS_REG))] "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)) && !(MEM_P (operands[0]) && MEM_P (operands[1]))" @@ -9113,9 +9108,9 @@ [(set (reg FLAGS_REG) (compare (any_or:SWI (match_operand:SWI 1 "nonimmediate_operand" "%0,0") - (match_operand:SWI 2 "" ",")) + (match_operand:SWI 2 "" ",m")) (const_int 0))) - (set (match_operand:SWI 0 "nonimmediate_operand" "=,m") + (set (match_operand:SWI 0 "nonimmediate_operand" "=m,") (any_or:SWI (match_dup 1) (match_dup 2)))] "ix86_match_ccmode (insn, CCNOmode) && ix86_binary_operator_ok (, mode, operands)" @@ -9154,8 +9149,8 @@ (define_insn "*qi_2_slp" [(set (reg FLAGS_REG) - (compare (any_or:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm") - (match_operand:QI 1 "general_operand" "qmn,qn")) + (compare (any_or:QI (match_operand:QI 0 "nonimmediate_operand" "+qm,q") + (match_operand:QI 1 "general_operand" "qn,m")) (const_int 0))) (set (strict_low_part (match_dup 0)) (any_or:QI (match_dup 0) (match_dup 1)))]